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| author | Eryk Brol <eryk.brol@amd.com> | 2020-06-19 14:42:09 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-08-17 14:08:34 -0400 |
| commit | bcc6aa61c82d4f12df3ecc884a9eef9d566edae9 (patch) | |
| tree | 7b5df12ff642e55f89fe0a7dbb2cfc98e255eb77 /drivers/gpu/drm/amd/display/dc/dc_dsc.h | |
| parent | 4bb23a544667a5c9f6dd158abf5158c120e1707f (diff) | |
| download | linux-stable-bcc6aa61c82d4f12df3ecc884a9eef9d566edae9.tar.gz linux-stable-bcc6aa61c82d4f12df3ecc884a9eef9d566edae9.tar.bz2 linux-stable-bcc6aa61c82d4f12df3ecc884a9eef9d566edae9.zip | |
drm/amd/display: Fix DSC force enable on SST
[why]
Previously when force enabling DSC on SST display we unknowingly
supressed lane count, which caused DSC to be enabled automatically.
[how]
By adding an additional flag to force enable DSC in dc_dsc.c DSC can
always be enabled with debugfs dsc_clock_en forced to 1
Cc: stable@vger.kernel.org
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_dsc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc_dsc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h index 3800340a5b4f..768ab38d41cf 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h @@ -51,6 +51,7 @@ struct dc_dsc_policy { int min_slice_height; // Must not be less than 8 uint32_t max_target_bpp; uint32_t min_target_bpp; + bool enable_dsc_when_not_needed; }; bool dc_dsc_parse_dsc_dpcd(const struct dc *dc, @@ -80,4 +81,6 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit); +void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable); + #endif |