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| author | Wenjing Liu <wenjing.liu@amd.com> | 2022-01-19 16:24:38 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-01-25 18:00:34 -0500 |
| commit | d9eb8fea6862e63421f7b9c93e32bef348488c41 (patch) | |
| tree | f2785c63d0ec9962fc43df825f7d7cc7dfb34a07 /drivers/gpu/drm/amd/display/dc/dc_types.h | |
| parent | 31d64b8219e057705d7a9debffcf6abbccb7781e (diff) | |
| download | linux-stable-d9eb8fea6862e63421f7b9c93e32bef348488c41.tar.gz linux-stable-d9eb8fea6862e63421f7b9c93e32bef348488c41.tar.bz2 linux-stable-d9eb8fea6862e63421f7b9c93e32bef348488c41.zip | |
drm/amd/display: Drop DCN for DP2.x logic
[Why & How]
DCN guard is not necessary for DP2.x relevant logic.
Drop them.
v2: squash in fix for misplaced #endif (Alex)
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Jerry Zuo <Jerry.Zuo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_types.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc_types.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 0285a4b38d05..48859d5fc172 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -395,14 +395,11 @@ struct dc_lttpr_caps { uint8_t max_link_rate; uint8_t phy_repeater_cnt; uint8_t max_ext_timeout; -#if defined(CONFIG_DRM_AMD_DC_DCN) union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding; union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates; -#endif uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1]; }; -#if defined(CONFIG_DRM_AMD_DC_DCN) struct dc_dongle_dfp_cap_ext { bool supported; uint16_t max_pixel_rate_in_mps; @@ -414,7 +411,6 @@ struct dc_dongle_dfp_cap_ext { struct dp_color_depth_caps ycbcr422_color_depth_caps; struct dp_color_depth_caps ycbcr420_color_depth_caps; }; -#endif struct dc_dongle_caps { /* dongle type (DP converter, CV smart dongle) */ @@ -429,10 +425,8 @@ struct dc_dongle_caps { bool is_dp_hdmi_ycbcr420_converter; uint32_t dp_hdmi_max_bpc; uint32_t dp_hdmi_max_pixel_clk_in_khz; -#if defined(CONFIG_DRM_AMD_DC_DCN) uint32_t dp_hdmi_frl_max_link_bw_in_kbps; struct dc_dongle_dfp_cap_ext dfp_cap_ext; -#endif }; /* Scaling format */ enum scaling_transformation { |