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author | Alvin Lee <alvin.lee2@amd.com> | 2023-05-18 11:30:44 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-09 12:41:22 -0400 |
commit | 0baae624630788862bbd654741929007971e9d5b (patch) | |
tree | c5caf4107b487c0578245aca1fac9ce7423e6ad3 /drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | |
parent | 49f26218c344741cb3eaa740b1e44e960551a87f (diff) | |
download | linux-stable-0baae624630788862bbd654741929007971e9d5b.tar.gz linux-stable-0baae624630788862bbd654741929007971e9d5b.tar.bz2 linux-stable-0baae624630788862bbd654741929007971e9d5b.zip |
drm/amd/display: Refactor fast update to use new HWSS build sequence
[Description]
- Refactor HW sequencer to use a build / execute sequence
- Also move gamma updates to become fast
v2: squash in build fix ("drm/amd/display: Fix guarding of 'if (dc->debug.visual_confirm)'")
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 54805802cbd5..42e9b6a529f6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -401,6 +401,10 @@ static const struct dc_plane_cap plane_cap = { } }; +static const struct dc_debug_options debug_defaults = { + .enable_legacy_fast_update = true, +}; + #define CTX ctx #define REG(reg) mm ## reg @@ -1071,6 +1075,7 @@ static bool dce100_resource_construct( dc->caps.dual_link_dvi = true; dc->caps.disable_dp_clk_share = true; dc->caps.extended_aux_timeout_support = false; + dc->debug = debug_defaults; for (i = 0; i < pool->base.pipe_count; i++) { pool->base.timing_generators[i] = |