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authorDing Wang <Ding.Wang@amd.com>2016-12-05 18:20:51 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 17:04:07 -0400
commite91dbe3dee1acae4909bcc33288d47a779e8b27f (patch)
treedd2bf9006bbfeb9b8b1b19156d71339c9bd991e4 /drivers/gpu/drm/amd/display/dc/dce110
parent13625c7bf328c9e201363eba3c3e5a15560c4ae9 (diff)
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drm/amd/display: Temporarily blocking interlacing mode until it's supported.
Signed-off-by: Ding Wang <Ding.Wang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce110')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 12a258763ef1..e70704d1ba87 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1117,6 +1117,10 @@ bool dce110_timing_generator_validate_timing(
if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE)
return false;
+ /* Temporarily blocking interlacing mode until it's supported */
+ if (timing->flags.INTERLACE == 1)
+ return false;
+
/* Check maximum number of pixels supported by Timing Generator
* (Currently will never fail, in order to fail needs display which
* needs more than 8192 horizontal and