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author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2017-05-15 08:31:51 -0400 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:07:12 -0400 |
commit | c34892144d38eddb4499ac425c24455b1e34dd61 (patch) | |
tree | 321ce50599f5a78808af4d868f6d8865e6e785d1 /drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | |
parent | aa7397dfd4cd2e31f007ad3adc08823afb40c25b (diff) | |
download | linux-stable-c34892144d38eddb4499ac425c24455b1e34dd61.tar.gz linux-stable-c34892144d38eddb4499ac425c24455b1e34dd61.tar.bz2 linux-stable-c34892144d38eddb4499ac425c24455b1e34dd61.zip |
drm/amd/display: dce 8 - 12 mem_input refactor to new style
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 75 |
1 files changed, 9 insertions, 66 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index b13abb025e1b..1276dabfb208 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -41,8 +41,7 @@ #include "dce/dce_clock_source.h" #include "dce/dce_clocks.h" #include "dce/dce_ipp.h" -#include "dce110/dce110_mem_input.h" -#include "dce120/dce120_mem_input.h" +#include "dce/dce_mem_input.h" #include "dce110/dce110_hw_sequencer.h" #include "dce120/dce120_hw_sequencer.h" @@ -376,51 +375,6 @@ struct output_pixel_processor *dce120_opp_create( return NULL; } -static const struct dce110_mem_input_reg_offsets dce120_mi_reg_offsets[] = { - { - .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), - .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL - - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), - .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL - - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), - .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL - - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), - .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL - - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE3_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), - .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL - - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE4_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - }, - { - .dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), - .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL - - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), - .pipe = (mmPIPE5_DMIF_BUFFER_CONTROL - - mmPIPE0_DMIF_BUFFER_CONTROL), - } -}; - static const struct bios_registers bios_regs = { .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) }; @@ -518,7 +472,7 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); + dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } @@ -708,27 +662,17 @@ static const struct dce_mem_input_mask mi_masks = { static struct mem_input *dce120_mem_input_create( struct dc_context *ctx, - uint32_t inst, - const struct dce110_mem_input_reg_offsets *offset) + uint32_t inst) { - struct dce110_mem_input *mem_input110 = - dm_alloc(sizeof(struct dce110_mem_input)); + struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); - if (!mem_input110) + if (!dce_mi) { + BREAK_TO_DEBUGGER(); return NULL; - - if (dce120_mem_input_construct(mem_input110, ctx, inst, offset)) { - struct mem_input *mi = &mem_input110->base; - - mi->regs = &mi_regs[inst]; - mi->shifts = &mi_shifts; - mi->masks = &mi_masks; - return mi; } - BREAK_TO_DEBUGGER(); - dm_free(mem_input110); - return NULL; + dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); + return &dce_mi->base; } static struct transform *dce120_transform_create( @@ -1007,8 +951,7 @@ static bool construct( goto controller_create_fail; } - pool->base.mis[i] = dce120_mem_input_create(ctx, - i, &dce120_mi_reg_offsets[i]); + pool->base.mis[i] = dce120_mem_input_create(ctx, i); if (pool->base.mis[i] == NULL) { BREAK_TO_DEBUGGER(); |