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| author | Yongqiang Sun <yongqiang.sun@amd.com> | 2017-06-26 16:25:10 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:08:32 -0400 |
| commit | 97416d4cbb9efab2eea7740fa4ce86b317da06c5 (patch) | |
| tree | a9c242ec7db172e399fdd1ccf7ba7316c2285319 /drivers/gpu/drm/amd/display/dc/dce120 | |
| parent | 7a8368e6f521871976f3d173f837dd921d06130d (diff) | |
| download | linux-stable-97416d4cbb9efab2eea7740fa4ce86b317da06c5.tar.gz linux-stable-97416d4cbb9efab2eea7740fa4ce86b317da06c5.tar.bz2 linux-stable-97416d4cbb9efab2eea7740fa4ce86b317da06c5.zip | |
drm/amd/display: set drr during program timing.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce120')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 03b21e9a1156..58a070debd58 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -441,15 +441,28 @@ void dce120_timing_generator_program_blanking( struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); CRTC_REG_UPDATE( - CRTC0_CRTC_H_TOTAL, - CRTC_H_TOTAL, - timing->h_total - 1); + CRTC0_CRTC_H_TOTAL, + CRTC_H_TOTAL, + timing->h_total - 1); CRTC_REG_UPDATE( CRTC0_CRTC_V_TOTAL, CRTC_V_TOTAL, timing->v_total - 1); + /* In case of V_TOTAL_CONTROL is on, make sure V_TOTAL_MAX and + * V_TOTAL_MIN are equal to V_TOTAL. + */ + CRTC_REG_UPDATE( + CRTC0_CRTC_V_TOTAL_MAX, + CRTC_V_TOTAL_MAX, + timing->v_total - 1); + + CRTC_REG_UPDATE( + CRTC0_CRTC_V_TOTAL_MIN, + CRTC_V_TOTAL_MIN, + timing->v_total - 1); + tmp1 = timing->h_total - (h_sync_start + timing->h_border_left); tmp2 = tmp1 + timing->h_addressable + |