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| author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2018-09-13 17:42:14 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-11-05 14:20:40 -0500 |
| commit | 24f7dd7ea98dc54fa45a0dd10c7a472e00ca01d4 (patch) | |
| tree | 0d1de64685041661d4b0b73708b85da62d461a88 /drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | |
| parent | 72942b3de8dadf92095cd14ca1aeb92c54280799 (diff) | |
| download | linux-stable-24f7dd7ea98dc54fa45a0dd10c7a472e00ca01d4.tar.gz linux-stable-24f7dd7ea98dc54fa45a0dd10c7a472e00ca01d4.tar.bz2 linux-stable-24f7dd7ea98dc54fa45a0dd10c7a472e00ca01d4.zip | |
drm/amd/display: move pplib/smu notification to dccg block
This is done to clear up the clock programming sequence
since the only time we need to notify pplib is after
clock update.
This also renames the clk block to dccg, at the moment
this block contains both clock management and dccg
functionality.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index d68f951f9869..76f58c6a6130 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -23,6 +23,7 @@ * */ +#include "../dce/dce_clocks.h" #include "dce/dce_8_0_d.h" #include "dce/dce_8_0_sh_mask.h" @@ -44,7 +45,6 @@ #include "dce/dce_ipp.h" #include "dce/dce_transform.h" #include "dce/dce_opp.h" -#include "dce/dce_clocks.h" #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" @@ -793,7 +793,7 @@ bool dce80_validate_bandwidth( { /* TODO implement when needed but for now hardcode max value*/ context->bw.dce.dispclk_khz = 681000; - context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER; + context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; return true; } |