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authorTony Cheng <tony.cheng@amd.com>2017-01-03 12:40:40 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 17:08:19 -0400
commit7fc698a0c0e5901923a6d6c04a59aceefffe4c9b (patch)
treef7eb089f41c6eb1cf624f34344e7bc9186befea1 /drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
parent4dfb0badee55bf163f4ce3307572cd4963c791d0 (diff)
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drm/amd/display: limit HBR3 support to Polaris and up
- also fix YCbCr420 supported on Polaris and up Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 56a63d985440..e2bfa7efce1c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -611,6 +611,14 @@ static struct input_pixel_processor *dce80_ipp_create(
return NULL;
}
+static const struct encoder_feature_support link_enc_feature = {
+ .max_hdmi_deep_color = COLOR_DEPTH_121212,
+ .max_hdmi_pixel_clock = 297000,
+ .flags.bits.IS_HBR2_CAPABLE = true,
+ .flags.bits.IS_TPS3_CAPABLE = true,
+ .flags.bits.IS_YCBCR_CAPABLE = true
+};
+
struct link_encoder *dce80_link_encoder_create(
const struct encoder_init_data *enc_init_data)
{
@@ -623,12 +631,11 @@ struct link_encoder *dce80_link_encoder_create(
if (dce110_link_encoder_construct(
enc110,
enc_init_data,
+ &link_enc_feature,
&link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1],
&link_enc_hpd_regs[enc_init_data->hpd_source])) {
- enc110->base.features.ycbcr420_supported = false;
- enc110->base.features.max_hdmi_pixel_clock = 297000;
return &enc110->base;
}