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| author | Vitaly Prosyak <vitaly.prosyak@amd.com> | 2017-10-05 10:45:50 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-10-21 16:49:18 -0400 |
| commit | 3411eac1a144ac5ad5a7ab994645724130bb2996 (patch) | |
| tree | 3a14d53c8f7ca09a3712e72d0a25288b748c5aec /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | |
| parent | be5a55dc3de9bc5764b3eb4ba6f743783584aa58 (diff) | |
| download | linux-stable-3411eac1a144ac5ad5a7ab994645724130bb2996.tar.gz linux-stable-3411eac1a144ac5ad5a7ab994645724130bb2996.tar.bz2 linux-stable-3411eac1a144ac5ad5a7ab994645724130bb2996.zip | |
drm/amd/display: [RV] bug in cm programming
When surface bigger then 10 bpc the output pixel
does not match to the required value.Update CRC's.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index 61e2a8919e9c..f88fd2e2e0aa 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -602,7 +602,7 @@ static void ippn10_enable_cm_block( struct transform *xfm_base) { struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base); - + REG_UPDATE(CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, 8); REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0); } |