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| author | Harry Wentland <harry.wentland@amd.com> | 2019-02-22 15:50:50 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-21 18:59:34 -0500 |
| commit | f7de96ee8b5f4d0d4ef7b00b8868049a6869a10f (patch) | |
| tree | 642f348d5233ecde53fc2422de386c9d2595f311 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | |
| parent | f789b0b82bf0aee36ce2bb4270aad617d16c3b6b (diff) | |
| download | linux-stable-f7de96ee8b5f4d0d4ef7b00b8868049a6869a10f.tar.gz linux-stable-f7de96ee8b5f4d0d4ef7b00b8868049a6869a10f.tar.bz2 linux-stable-f7de96ee8b5f4d0d4ef7b00b8868049a6869a10f.zip | |
drm/amd/display: Add DCN2 DPP
Add support to program the DCN2 DPP (Multiple pipe and plane combine)
HW Blocks:
+--------+
| DPP |
+--------+
|
v
+--------+
| MPC |
+--------+
|
v
+-------+
| OPP |
+-------+
|
v
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index 882bcc5a40f6..aa0c7a7d13a0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -731,6 +731,10 @@ void dpp1_full_bypass(struct dpp *dpp_base) /* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */ if (dpp->tf_mask->CM_BYPASS_EN) REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1); +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + else + REG_SET(CM_CONTROL, 0, CM_BYPASS, 1); +#endif /* Setting degamma bypass for now */ REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0); |