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| author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2017-07-21 17:35:16 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:15:28 -0400 |
| commit | 516666318fe1f427ab81e2ebe45d116a9667c3b5 (patch) | |
| tree | eaacca1377354237ee6540caf0d6d93081eae049 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | |
| parent | f811fd5a66a3e69cdc184accfe189de5a1f6dba4 (diff) | |
| download | linux-stable-516666318fe1f427ab81e2ebe45d116a9667c3b5.tar.gz linux-stable-516666318fe1f427ab81e2ebe45d116a9667c3b5.tar.bz2 linux-stable-516666318fe1f427ab81e2ebe45d116a9667c3b5.zip | |
drm/amd/display: support for updated register headers on DCN
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c index 53dd9a9593f0..ee12f671d8ea 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c @@ -472,11 +472,18 @@ static bool ippn10_cursor_program_control( bool pixel_data_invert, enum dc_cursor_color_format color_format) { - REG_SET_2(CURSOR_SETTINS, 0, - /* no shift of the cursor HDL schedule */ - CURSOR0_DST_Y_OFFSET, 0, - /* used to shift the cursor chunk request deadline */ - CURSOR0_CHUNK_HDL_ADJUST, 3); + if (REG(CURSOR_SETTINS)) + REG_SET_2(CURSOR_SETTINS, 0, + /* no shift of the cursor HDL schedule */ + CURSOR0_DST_Y_OFFSET, 0, + /* used to shift the cursor chunk request deadline */ + CURSOR0_CHUNK_HDL_ADJUST, 3); + else + REG_SET_2(CURSOR_SETTINGS, 0, + /* no shift of the cursor HDL schedule */ + CURSOR0_DST_Y_OFFSET, 0, + /* used to shift the cursor chunk request deadline */ + CURSOR0_CHUNK_HDL_ADJUST, 3); REG_UPDATE_2(CURSOR0_CONTROL, CUR0_MODE, color_format, |