diff options
author | Anthony Koo <Anthony.Koo@amd.com> | 2017-08-03 09:59:23 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:16:20 -0400 |
commit | d66cf5f5013a4268057bcb92d301d010268ea27f (patch) | |
tree | 3bad6df8f6eb551dacb8963036701f03f677a54d /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | |
parent | 665da60f23d8c6bda5431529a73be49b3b9d97cb (diff) | |
download | linux-stable-d66cf5f5013a4268057bcb92d301d010268ea27f.tar.gz linux-stable-d66cf5f5013a4268057bcb92d301d010268ea27f.tar.bz2 linux-stable-d66cf5f5013a4268057bcb92d301d010268ea27f.zip |
drm/amd/display: implement DXGI Gamma Ramps
Support for gamma correction ramp in Floating Point format
Signed-off-by: Anthony Koo <anthony.koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c index ee12f671d8ea..8ee830522148 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c @@ -910,13 +910,16 @@ static void ippn10_program_input_lut( CM_IGAM_LUT_FORMAT_B, 3); // Start at index 0 of IGAM LUT REG_UPDATE(CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, 0); - for (i = 0; i < INPUT_LUT_ENTRIES; i++) { + for (i = 0; i < gamma->num_entries; i++) { REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, - gamma->red[i]); + dal_fixed31_32_round( + gamma->entries.red[i])); REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, - gamma->green[i]); + dal_fixed31_32_round( + gamma->entries.green[i])); REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, - gamma->blue[i]); + dal_fixed31_32_round( + gamma->entries.blue[i])); } // Power off LUT memory REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 0); |