diff options
| author | Yue Hin Lau <Yuehin.Lau@amd.com> | 2017-11-09 15:56:25 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-06 12:48:07 -0500 |
| commit | 125d10a23347269abf88b05f919d33f4120b82cb (patch) | |
| tree | 7733f05c16d4d4c5c2598b8112fc47c4ce6f9c8f /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | |
| parent | 480bd0cf450bdabeca49f135e6f1c2a58d1bb957 (diff) | |
| download | linux-stable-125d10a23347269abf88b05f919d33f4120b82cb.tar.gz linux-stable-125d10a23347269abf88b05f919d33f4120b82cb.tar.bz2 linux-stable-125d10a23347269abf88b05f919d33f4120b82cb.zip | |
drm/amd/display: fix opp header register define
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h index 4b1e51050d33..f3c298ec37fb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h @@ -46,6 +46,16 @@ #define OPP_REG_LIST_DCN10(id) \ OPP_REG_LIST_DCN(id) +#define OPP_COMMON_REG_VARIABLE_LIST \ + uint32_t FMT_BIT_DEPTH_CONTROL; \ + uint32_t FMT_CONTROL; \ + uint32_t FMT_DITHER_RAND_R_SEED; \ + uint32_t FMT_DITHER_RAND_G_SEED; \ + uint32_t FMT_DITHER_RAND_B_SEED; \ + uint32_t FMT_CLAMP_CNTL; \ + uint32_t FMT_DYNAMIC_EXP_CNTL; \ + uint32_t FMT_MAP420_MEMORY_CONTROL; + #define OPP_MASK_SH_LIST_DCN(mask_sh) \ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \ @@ -97,6 +107,10 @@ type FMT_MAP420MEM_PWR_FORCE; \ type FMT_STEREOSYNC_OVERRIDE; +struct dcn10_opp_registers { + OPP_COMMON_REG_VARIABLE_LIST +}; + struct dcn10_opp_shift { OPP_DCN10_REG_FIELD_LIST(uint8_t) }; @@ -105,17 +119,6 @@ struct dcn10_opp_mask { OPP_DCN10_REG_FIELD_LIST(uint32_t) }; -struct dcn10_opp_registers { - uint32_t FMT_BIT_DEPTH_CONTROL; - uint32_t FMT_CONTROL; - uint32_t FMT_DITHER_RAND_R_SEED; - uint32_t FMT_DITHER_RAND_G_SEED; - uint32_t FMT_DITHER_RAND_B_SEED; - uint32_t FMT_CLAMP_CNTL; - uint32_t FMT_DYNAMIC_EXP_CNTL; - uint32_t FMT_MAP420_MEMORY_CONTROL; -}; - struct dcn10_opp { struct output_pixel_processor base; |