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| author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2017-07-21 17:35:16 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:15:28 -0400 |
| commit | 516666318fe1f427ab81e2ebe45d116a9667c3b5 (patch) | |
| tree | eaacca1377354237ee6540caf0d6d93081eae049 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | |
| parent | f811fd5a66a3e69cdc184accfe189de5a1f6dba4 (diff) | |
| download | linux-stable-516666318fe1f427ab81e2ebe45d116a9667c3b5.tar.gz linux-stable-516666318fe1f427ab81e2ebe45d116a9667c3b5.tar.bz2 linux-stable-516666318fe1f427ab81e2ebe45d116a9667c3b5.zip | |
drm/amd/display: support for updated register headers on DCN
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h index de0b631736bb..d9d66a4afb19 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h @@ -123,7 +123,6 @@ SRI(CM_MEM_PWR_CTRL, CM, id), \ SRI(CM_RGAM_LUT_DATA, CM, id) - #define OPP_MASK_SH_LIST_DCN(mask_sh) \ OPP_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ @@ -357,6 +356,16 @@ OPP_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh) #define OPP_DCN10_REG_FIELD_LIST(type) \ + type DPG_EN; \ + type DPG_MODE; \ + type DPG_VRES; \ + type DPG_HRES; \ + type DPG_COLOUR0_R_CR; \ + type DPG_COLOUR1_R_CR; \ + type DPG_COLOUR0_B_CB; \ + type DPG_COLOUR1_B_CB; \ + type DPG_COLOUR0_G_Y; \ + type DPG_COLOUR1_G_Y; \ type CM_OCSC_C11; \ type CM_OCSC_C12; \ type CM_OCSC_C13; \ @@ -594,6 +603,10 @@ struct dcn10_opp_mask { }; struct dcn10_opp_registers { + uint32_t DPG_CONTROL; + uint32_t DPG_COLOUR_B_CB; + uint32_t DPG_COLOUR_G_Y; + uint32_t DPG_COLOUR_R_CR; uint32_t CM_OCSC_C11_C12; uint32_t CM_OCSC_C13_C14; uint32_t CM_OCSC_C21_C22; |