diff options
| author | Eric Bernstein <eric.bernstein@amd.com> | 2017-10-31 11:52:25 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-06 12:47:28 -0500 |
| commit | 6d56c5733282adb608795f1afe763988ba035218 (patch) | |
| tree | 51def75246a6a1c4e2cbd0f666d1e1f57ef37bb1 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | |
| parent | 63340ae9a612063975d661369d07bae499e5e8ba (diff) | |
| download | linux-stable-6d56c5733282adb608795f1afe763988ba035218.tar.gz linux-stable-6d56c5733282adb608795f1afe763988ba035218.tar.bz2 linux-stable-6d56c5733282adb608795f1afe763988ba035218.zip | |
drm/amd/display: Add OPP DPG blank function
Added a function to blank data using OPP DPG.
Clean up code to prepare for pseudocode review with HW.
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 45 |
1 files changed, 6 insertions, 39 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h index 790ce6014832..cdb220ed858e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h @@ -78,36 +78,14 @@ type DPG_MODE; \ type DPG_VRES; \ type DPG_HRES; \ + type DPG_ACTIVE_WIDTH; \ + type DPG_ACTIVE_HEIGHT; \ type DPG_COLOUR0_R_CR; \ type DPG_COLOUR1_R_CR; \ type DPG_COLOUR0_B_CB; \ type DPG_COLOUR1_B_CB; \ type DPG_COLOUR0_G_Y; \ type DPG_COLOUR1_G_Y; \ - type CM_OCSC_C11; \ - type CM_OCSC_C12; \ - type CM_OCSC_C13; \ - type CM_OCSC_C14; \ - type CM_OCSC_C21; \ - type CM_OCSC_C22; \ - type CM_OCSC_C23; \ - type CM_OCSC_C24; \ - type CM_OCSC_C31; \ - type CM_OCSC_C32; \ - type CM_OCSC_C33; \ - type CM_OCSC_C34; \ - type CM_COMB_C11; \ - type CM_COMB_C12; \ - type CM_COMB_C13; \ - type CM_COMB_C14; \ - type CM_COMB_C21; \ - type CM_COMB_C22; \ - type CM_COMB_C23; \ - type CM_COMB_C24; \ - type CM_COMB_C31; \ - type CM_COMB_C32; \ - type CM_COMB_C33; \ - type CM_COMB_C34; \ type FMT_TRUNCATE_EN; \ type FMT_TRUNCATE_DEPTH; \ type FMT_TRUNCATE_MODE; \ @@ -129,33 +107,22 @@ type FMT_DYNAMIC_EXP_EN; \ type FMT_DYNAMIC_EXP_MODE; \ type FMT_MAP420MEM_PWR_FORCE; \ - type FMT_STEREOSYNC_OVERRIDE + type FMT_STEREOSYNC_OVERRIDE; struct dcn10_opp_shift { - OPP_DCN10_REG_FIELD_LIST(uint8_t); + OPP_DCN10_REG_FIELD_LIST(uint8_t) }; struct dcn10_opp_mask { - OPP_DCN10_REG_FIELD_LIST(uint32_t); + OPP_DCN10_REG_FIELD_LIST(uint32_t) }; struct dcn10_opp_registers { uint32_t DPG_CONTROL; + uint32_t DPG_DIMENSIONS; uint32_t DPG_COLOUR_B_CB; uint32_t DPG_COLOUR_G_Y; uint32_t DPG_COLOUR_R_CR; - uint32_t CM_OCSC_C11_C12; - uint32_t CM_OCSC_C13_C14; - uint32_t CM_OCSC_C21_C22; - uint32_t CM_OCSC_C23_C24; - uint32_t CM_OCSC_C31_C32; - uint32_t CM_OCSC_C33_C34; - uint32_t CM_COMB_C11_C12; - uint32_t CM_COMB_C13_C14; - uint32_t CM_COMB_C21_C22; - uint32_t CM_COMB_C23_C24; - uint32_t CM_COMB_C31_C32; - uint32_t CM_COMB_C33_C34; uint32_t FMT_BIT_DEPTH_CONTROL; uint32_t FMT_CONTROL; uint32_t FMT_DITHER_RAND_R_SEED; |