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| author | Tony Cheng <tony.cheng@amd.com> | 2017-07-22 21:58:08 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:15:32 -0400 |
| commit | 7db90a6b58761577596499ddd90f3c5ace2b716d (patch) | |
| tree | 685292bfc1e3ccaf1a8dced885401c72125cb219 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | |
| parent | 8748068764e7a50ac787c1c17f402f3fbbe97ccc (diff) | |
| download | linux-stable-7db90a6b58761577596499ddd90f3c5ace2b716d.tar.gz linux-stable-7db90a6b58761577596499ddd90f3c5ace2b716d.tar.bz2 linux-stable-7db90a6b58761577596499ddd90f3c5ace2b716d.zip | |
drm/amd/display: move ocsc programming from opp to dpp
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yuehin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h index d9d66a4afb19..900298d6e5b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h @@ -46,21 +46,8 @@ #define OPP_REG_LIST_DCN10(id) \ OPP_REG_LIST_DCN(id), \ - SRI(CM_OCSC_C11_C12, CM, id), \ - SRI(CM_OCSC_C13_C14, CM, id), \ - SRI(CM_OCSC_C21_C22, CM, id), \ - SRI(CM_OCSC_C23_C24, CM, id), \ - SRI(CM_OCSC_C31_C32, CM, id), \ - SRI(CM_OCSC_C33_C34, CM, id), \ - SRI(CM_COMB_C11_C12, CM, id), \ - SRI(CM_COMB_C13_C14, CM, id), \ - SRI(CM_COMB_C21_C22, CM, id), \ - SRI(CM_COMB_C23_C24, CM, id), \ - SRI(CM_COMB_C31_C32, CM, id), \ - SRI(CM_COMB_C33_C34, CM, id), \ SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id), \ SRI(CM_RGAM_CONTROL, CM, id), \ - SRI(CM_OCSC_CONTROL, CM, id), \ SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \ SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \ SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \ @@ -151,32 +138,7 @@ #define OPP_MASK_SH_LIST_DCN10(mask_sh) \ OPP_MASK_SH_LIST_DCN(mask_sh), \ OPP_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C13, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C14, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C21, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C22, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C23, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C24, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C31, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C32, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \ - OPP_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \ - OPP_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh), \ - OPP_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh), \ - OPP_SF(CM0_CM_COMB_C13_C14, CM_COMB_C13, mask_sh), \ - OPP_SF(CM0_CM_COMB_C13_C14, CM_COMB_C14, mask_sh), \ - OPP_SF(CM0_CM_COMB_C21_C22, CM_COMB_C21, mask_sh), \ - OPP_SF(CM0_CM_COMB_C21_C22, CM_COMB_C22, mask_sh), \ - OPP_SF(CM0_CM_COMB_C23_C24, CM_COMB_C23, mask_sh), \ - OPP_SF(CM0_CM_COMB_C23_C24, CM_COMB_C24, mask_sh), \ - OPP_SF(CM0_CM_COMB_C31_C32, CM_COMB_C31, mask_sh), \ - OPP_SF(CM0_CM_COMB_C31_C32, CM_COMB_C32, mask_sh), \ - OPP_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh), \ - OPP_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh), \ OPP_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \ - OPP_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \ @@ -414,7 +376,6 @@ type FMT_DYNAMIC_EXP_EN; \ type FMT_DYNAMIC_EXP_MODE; \ type FMT_MAP420MEM_PWR_FORCE; \ - type CM_OCSC_MODE; \ type CM_RGAM_RAMB_EXP_REGION_START_B; \ type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ type CM_RGAM_RAMB_EXP_REGION_START_G; \ @@ -630,7 +591,6 @@ struct dcn10_opp_registers { uint32_t FMT_CLAMP_CNTL; uint32_t FMT_DYNAMIC_EXP_CNTL; uint32_t FMT_MAP420_MEMORY_CONTROL; - uint32_t CM_OCSC_CONTROL; uint32_t CM_RGAM_RAMB_START_CNTL_B; uint32_t CM_RGAM_RAMB_START_CNTL_G; uint32_t CM_RGAM_RAMB_START_CNTL_R; |