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| author | Qingqing Zhuo <Qingqing.Zhuo@amd.com> | 2023-08-03 00:53:11 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-08-30 15:51:13 -0400 |
| commit | 473eb67cf117ac0ac0f31bc4511cec6418b97d04 (patch) | |
| tree | 7713373331c4a152545cdb569ded0b65450876bf /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | |
| parent | 9d1870a7a4c73c781af03937a1bfa72aa7a4c7ea (diff) | |
| download | linux-stable-473eb67cf117ac0ac0f31bc4511cec6418b97d04.tar.gz linux-stable-473eb67cf117ac0ac0f31bc4511cec6418b97d04.tar.bz2 linux-stable-473eb67cf117ac0ac0f31bc4511cec6418b97d04.zip | |
drm/amd/display: Update DCN10 for DCN35 support
[Why & How]
Update DCN10 files for DCN35 usage.
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h index 9d5e2a7848dd..085b269c654f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h @@ -188,6 +188,9 @@ struct dcn10_stream_enc_registers { uint32_t HDMI_GENERIC_PACKET_CONTROL10; uint32_t DIG_CLOCK_PATTERN; uint32_t DIG_FIFO_CTRL0; + uint32_t DIG_FE_CLK_CNTL; + uint32_t DIG_FE_EN_CNTL; + uint32_t STREAM_MAPPER_CONTROL; }; @@ -576,13 +579,25 @@ struct dcn10_stream_enc_registers { type DIG_FIFO_RESET;\ type DIG_FIFO_RESET_DONE +#define SE_REG_FIELD_LIST_DCN3_5_COMMON(type) \ + type DIG_FE_CLK_EN;\ + type DIG_FE_MODE;\ + type DIG_FE_SOFT_RESET;\ + type DIG_FE_ENABLE;\ + type DIG_FE_SYMCLK_FE_G_CLOCK_ON;\ + type DIG_FE_DISPCLK_G_CLOCK_ON;\ + type DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON;\ + type DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON;\ + type DIG_FE_SOCCLK_G_AFMT_CLOCK_ON;\ + type DIG_STREAM_LINK_TARGET + struct dcn10_stream_encoder_shift { SE_REG_FIELD_LIST_DCN1_0(uint8_t); uint8_t HDMI_ACP_SEND; SE_REG_FIELD_LIST_DCN2_0(uint8_t); SE_REG_FIELD_LIST_DCN3_0(uint8_t); SE_REG_FIELD_LIST_DCN3_2(uint8_t); - + SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t); }; struct dcn10_stream_encoder_mask { @@ -591,7 +606,7 @@ struct dcn10_stream_encoder_mask { SE_REG_FIELD_LIST_DCN2_0(uint32_t); SE_REG_FIELD_LIST_DCN3_0(uint32_t); SE_REG_FIELD_LIST_DCN3_2(uint32_t); - + SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t); }; struct dcn10_stream_encoder { |