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| author | Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2023-03-11 09:11:29 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-03-31 11:18:53 -0400 |
| commit | d29fb7baab09b6a1dc484c9c67933253883e770a (patch) | |
| tree | bee4c019554a25c06057327785c149ae23db2f79 /drivers/gpu/drm/amd/display/dc/dcn10 | |
| parent | 9c224e058dd9ae9b03602d6c86d44f0d11e21ba3 (diff) | |
| download | linux-stable-d29fb7baab09b6a1dc484c9c67933253883e770a.tar.gz linux-stable-d29fb7baab09b6a1dc484c9c67933253883e770a.tar.bz2 linux-stable-d29fb7baab09b6a1dc484c9c67933253883e770a.zip | |
drm/amd/display: Add NULL plane_state check for cursor disable logic
[Why]
While scanning the top_pipe connections we can run into a case where
the bottom pipe is still connected to a top_pipe but with a NULL
plane_state.
[How]
Treat a NULL plane_state the same as the plane being invisible for
pipe cursor disable logic.
Cc: stable@vger.kernel.org
Cc: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 7f9cceb49f4e..46ca88741cb8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -3385,7 +3385,9 @@ static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx) for (test_pipe = pipe_ctx->top_pipe; test_pipe; test_pipe = test_pipe->top_pipe) { // Skip invisible layer and pipe-split plane on same layer - if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer) + if (!test_pipe->plane_state || + !test_pipe->plane_state->visible || + test_pipe->plane_state->layer_index == cur_layer) continue; r2 = test_pipe->plane_res.scl_data.recout; |