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| author | Wesley Chalmers <Wesley.Chalmers@amd.com> | 2021-05-06 17:16:00 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-06-08 12:22:42 -0400 |
| commit | 39a1355feff934d967240f2212f5a25f9f6b1357 (patch) | |
| tree | 80ff9fa63615fb353ea56ebb440df9359468051e /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | |
| parent | b4d56e0c508b2ad847aeff5691f67bd2a40034ec (diff) | |
| download | linux-stable-39a1355feff934d967240f2212f5a25f9f6b1357.tar.gz linux-stable-39a1355feff934d967240f2212f5a25f9f6b1357.tar.bz2 linux-stable-39a1355feff934d967240f2212f5a25f9f6b1357.zip | |
drm/amd/display: Add interface for ADD & DROP PIXEL Registers
[WHY]
HW has handed down a new sequence that requires access to these
registers.
v2: squash in DCN3.1 fixes (Alex)
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c index 5679983158e2..5999b2da3a01 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c @@ -105,6 +105,30 @@ void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, DCCG_FIFO_ERRDET_OVR_EN, en ? 1 : 0); } +void dccg2_otg_add_pixel(struct dccg *dccg, + uint32_t otg_inst) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], + OTG_ADD_PIXEL[otg_inst], 0, + OTG_DROP_PIXEL[otg_inst], 0); + REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], + OTG_ADD_PIXEL[otg_inst], 1); +} + +void dccg2_otg_drop_pixel(struct dccg *dccg, + uint32_t otg_inst) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], + OTG_ADD_PIXEL[otg_inst], 0, + OTG_DROP_PIXEL[otg_inst], 0); + REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], + OTG_DROP_PIXEL[otg_inst], 1); +} + void dccg2_init(struct dccg *dccg) { } @@ -113,6 +137,8 @@ static const struct dccg_funcs dccg2_funcs = { .update_dpp_dto = dccg2_update_dpp_dto, .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, + .otg_add_pixel = dccg2_otg_add_pixel, + .otg_drop_pixel = dccg2_otg_drop_pixel, .dccg_init = dccg2_init }; |