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| author | Jun Lei <Jun.Lei@amd.com> | 2019-07-15 10:41:47 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-15 10:53:43 -0500 |
| commit | f7f38ffef56b0138f902efd261a6d90680fec2d3 (patch) | |
| tree | 09828e5dca528aab9256bc99a6d81dfc3dca872a /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | |
| parent | 9adc8050bf3ca3e49c65e13259a4c310640542f1 (diff) | |
| download | linux-stable-f7f38ffef56b0138f902efd261a6d90680fec2d3.tar.gz linux-stable-f7f38ffef56b0138f902efd261a6d90680fec2d3.tar.bz2 linux-stable-f7f38ffef56b0138f902efd261a6d90680fec2d3.zip | |
drm/amd/display: fixup DPP programming sequence
[why]
DC does not correct account for the fact that DPP DTO is double buffered while DPP ref is not.
This means that when DPP ref clock is lowered when it's "safe to lower", the DPP blocks that need
an increased divider will temporarily have actual DPP clock drop below minimum while DTO
double buffering takes effect. This results in temporary underflow.
[how]
To fix this, DPP clock cannot be programmed atomically, but rather be broken up into the DTO and the
ref. Each has a separate "safe to lower" logic. When doing "prepare" the ref and dividers may only increase.
When doing "optimize", both may decrease. It is guaranteed that we won't exceed max DPP clock because
we do not use dividers larger than 1.
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 31 |
1 files changed, 27 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c index 31aa6ee5cd5b..16476ed25536 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c @@ -44,12 +44,16 @@ #define DC_LOGGER \ dccg->ctx->logger -void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) +void dccg2_update_dpp_dto(struct dccg *dccg, + int dpp_inst, + int req_dppclk, + bool reduce_divider_only) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); if (dccg->ref_dppclk && req_dppclk) { int ref_dppclk = dccg->ref_dppclk; + int current_phase, current_modulo; ASSERT(req_dppclk <= ref_dppclk); /* need to clamp to 8 bits */ @@ -61,9 +65,28 @@ void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) if (req_dppclk > ref_dppclk) req_dppclk = ref_dppclk; } - REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, - DPPCLK0_DTO_PHASE, req_dppclk, - DPPCLK0_DTO_MODULO, ref_dppclk); + + REG_GET_2(DPPCLK_DTO_PARAM[dpp_inst], + DPPCLK0_DTO_PHASE, ¤t_phase, + DPPCLK0_DTO_MODULO, ¤t_modulo); + + if (reduce_divider_only) { + // requested phase/modulo greater than current + if (req_dppclk * current_modulo >= current_phase * ref_dppclk) { + REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, + DPPCLK0_DTO_PHASE, req_dppclk, + DPPCLK0_DTO_MODULO, ref_dppclk); + } else { + REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, + DPPCLK0_DTO_PHASE, current_phase, + DPPCLK0_DTO_MODULO, current_modulo); + } + } else { + REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, + DPPCLK0_DTO_PHASE, req_dppclk, + DPPCLK0_DTO_MODULO, ref_dppclk); + } + REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 1); } else { |