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| author | Saaem Rizvi <syedsaaem.rizvi@amd.com> | 2023-05-09 14:41:59 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-09 10:42:58 -0400 |
| commit | 3e8d74cb128fb1a4d56270ffbecea6056c55739a (patch) | |
| tree | 230bbf7aaab6e757e903e9b12059cccb5fc01bf3 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | |
| parent | 91b38ca1b331ef1af3b77e2ffdb41654e0fba127 (diff) | |
| download | linux-stable-3e8d74cb128fb1a4d56270ffbecea6056c55739a.tar.gz linux-stable-3e8d74cb128fb1a4d56270ffbecea6056c55739a.tar.bz2 linux-stable-3e8d74cb128fb1a4d56270ffbecea6056c55739a.zip | |
drm/amd/display: Trigger DIO FIFO resync on commit streams
[WHY]
Currently, there is an intermittent issue where a screen can either go
blank or be corrupted.
[HOW]
To resolve the issue we trigger the ramping logic for DIO FIFO so that
it goes back up to the correct speed.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Saaem Rizvi <syedsaaem.rizvi@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h index 7bdc146f7cb5..c8602bcfa393 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h @@ -208,7 +208,9 @@ #define DCCG314_REG_FIELD_LIST(type) \ type DSCCLK3_DTO_PHASE;\ type DSCCLK3_DTO_MODULO;\ - type DSCCLK3_DTO_ENABLE; + type DSCCLK3_DTO_ENABLE;\ + type DENTIST_DISPCLK_RDIVIDER;\ + type DENTIST_DISPCLK_WDIVIDER; #define DCCG32_REG_FIELD_LIST(type) \ type DPSTREAMCLK0_EN;\ |