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| author | Jake Wang <haonan.wang2@amd.com> | 2021-09-23 00:52:43 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-10-19 17:20:02 -0400 |
| commit | bda24462578ca2b0538d9257509070708ce41acc (patch) | |
| tree | 0777289d244a4f418588280ecc496b6f7c4b2de1 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | |
| parent | aacdc9d07ecd2d119229dbd59784c7aea4f3aed3 (diff) | |
| download | linux-stable-bda24462578ca2b0538d9257509070708ce41acc.tar.gz linux-stable-bda24462578ca2b0538d9257509070708ce41acc.tar.bz2 linux-stable-bda24462578ca2b0538d9257509070708ce41acc.zip | |
drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le
[Why & How]
Disable dpstreamclk, symclk32_se, and symclk32_le when not in use.
Reviewed-by: Ariel Bernstein <eric.yang2@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h index f6f2d48a70c1..4098669a0c1f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h @@ -178,7 +178,16 @@ type DSCCLK2_DTO_MODULO;\ type DSCCLK0_DTO_ENABLE;\ type DSCCLK1_DTO_ENABLE;\ - type DSCCLK2_DTO_ENABLE; + type DSCCLK2_DTO_ENABLE;\ + type SYMCLK32_ROOT_SE0_GATE_DISABLE;\ + type SYMCLK32_ROOT_SE1_GATE_DISABLE;\ + type SYMCLK32_ROOT_SE2_GATE_DISABLE;\ + type SYMCLK32_ROOT_SE3_GATE_DISABLE;\ + type SYMCLK32_ROOT_LE0_GATE_DISABLE;\ + type SYMCLK32_ROOT_LE1_GATE_DISABLE;\ + type DPSTREAMCLK_ROOT_GATE_DISABLE;\ + type DPSTREAMCLK_GATE_DISABLE; + struct dccg_shift { @@ -219,6 +228,10 @@ struct dccg_registers { uint32_t DSCCLK0_DTO_PARAM; uint32_t DSCCLK1_DTO_PARAM; uint32_t DSCCLK2_DTO_PARAM; + uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE; + uint32_t DPSTREAMCLK_GATE_DISABLE; + uint32_t DCCG_GATE_DISABLE_CNTL3; + }; struct dcn_dccg { |