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author | Leo (Hanghong) Ma <hanghong.ma@amd.com> | 2019-09-06 09:49:19 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2019-11-13 15:29:43 -0500 |
commit | ae8cf9774e3a609066b277c3742c3551564fb079 (patch) | |
tree | c1db2fa9132cc3c28d00b5aa0ca465accfdcfb9c /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c | |
parent | eb7d81af3c209b5135ec4402adf4e0cd5482b338 (diff) | |
download | linux-stable-ae8cf9774e3a609066b277c3742c3551564fb079.tar.gz linux-stable-ae8cf9774e3a609066b277c3742c3551564fb079.tar.bz2 linux-stable-ae8cf9774e3a609066b277c3742c3551564fb079.zip |
drm/amd/display: Add some hardware status in DTN log debugfs
[Why]
For debug purpose, we need to check the following hardware status
in DTN log debugfs:
1.dpp & hubp clock enable;
2.crtc blank enable;
3.link phy status;
[How]
Add the upper information in the amdgpu_dm_dtn_log debugfs.
For CRTC blanked status, since DCN2 and greater reports it on the OPP
instead of OTG, we patch it in after calling optc1_read_otg_states.
Ideally, this should be done in the DCN version specific function hooks.
It has been left as a TODO item.
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c index e476f27aa3a9..0e0306d84cd8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c @@ -203,6 +203,7 @@ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s) REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en); REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow); REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); + REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); } #endif |