diff options
| author | Jake Wang <haonan.wang2@amd.com> | 2021-09-23 00:52:43 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-10-19 17:20:02 -0400 |
| commit | bda24462578ca2b0538d9257509070708ce41acc (patch) | |
| tree | 0777289d244a4f418588280ecc496b6f7c4b2de1 /drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h | |
| parent | aacdc9d07ecd2d119229dbd59784c7aea4f3aed3 (diff) | |
| download | linux-stable-bda24462578ca2b0538d9257509070708ce41acc.tar.gz linux-stable-bda24462578ca2b0538d9257509070708ce41acc.tar.bz2 linux-stable-bda24462578ca2b0538d9257509070708ce41acc.zip | |
drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le
[Why & How]
Disable dpstreamclk, symclk32_se, and symclk32_le when not in use.
Reviewed-by: Ariel Bernstein <eric.yang2@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h index 61b457ab790d..602bf461298b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h @@ -65,7 +65,8 @@ SR(DSCCLK0_DTO_PARAM),\ SR(DSCCLK1_DTO_PARAM),\ SR(DSCCLK2_DTO_PARAM),\ - SR(DSCCLK_DTO_CTRL) + SR(DSCCLK_DTO_CTRL),\ + SR(DCCG_GATE_DISABLE_CNTL3) #define DCCG_MASK_SH_LIST_DCN31(mask_sh) \ @@ -132,7 +133,16 @@ DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\ DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, mask_sh),\ DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, mask_sh),\ - DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh) + DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh) + @@ -144,6 +154,11 @@ struct dccg *dccg31_create( void dccg31_init(struct dccg *dccg); +void dccg31_set_dpstreamclk( + struct dccg *dccg, + enum hdmistreamclk_source src, + int otg_inst); + void dccg31_enable_symclk32_se( struct dccg *dccg, int hpo_se_inst, |