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| author | Aurabindo Pillai <aurabindo.pillai@amd.com> | 2022-02-23 17:48:45 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-03 16:43:38 -0400 |
| commit | d3dfceb58de5f897640cdd424f6c2538d9514367 (patch) | |
| tree | 845cec73becf5b2217e701518b68897b5928a1f7 /drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h | |
| parent | 235c67634230b0f9ad8c0185272fed36c892b1c4 (diff) | |
| download | linux-stable-d3dfceb58de5f897640cdd424f6c2538d9514367.tar.gz linux-stable-d3dfceb58de5f897640cdd424f6c2538d9514367.tar.bz2 linux-stable-d3dfceb58de5f897640cdd424f6c2538d9514367.zip | |
drm/amd/display: Add dependant changes for DCN32/321
[Why&How]
This patch adds necessary changes needed in DC files outside DCN32/321
specific tree
v2: squash in updates (Alex)
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h index f158c1ea214b..80bd80707991 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h @@ -28,10 +28,6 @@ #include "dcn30/dcn30_dccg.h" -#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\ - .field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix - - #define DCCG_REG_LIST_DCN31() \ SR(DPPCLK_DTO_CTRL),\ DCCG_SRII(DTO_PARAM, DPPCLK, 0),\ @@ -124,6 +120,10 @@ DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 1, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 2, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 3, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\ DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh), \ @@ -163,7 +163,7 @@ void dccg31_init(struct dccg *dccg); void dccg31_set_dpstreamclk( struct dccg *dccg, - enum hdmistreamclk_source src, + enum streamclk_source src, int otg_inst); void dccg31_enable_symclk32_se( @@ -194,8 +194,4 @@ void dccg31_set_audio_dtbclk_dto( struct dccg *dccg, const struct dtbclk_dto_params *params); -void dccg31_set_hdmistreamclk( - struct dccg *dccg, - enum hdmistreamclk_source src); - #endif //__DCN31_DCCG_H__ |