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| author | Austin Zheng <austin.zheng@amd.com> | 2023-06-07 12:20:38 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-23 15:43:32 -0400 |
| commit | 2bf0ce3bec8b22e4bac828aeaeade15884fa0f5c (patch) | |
| tree | 9f970aa75c35270b08e11268e2f3c70be124a2d9 /drivers/gpu/drm/amd/display/dc/dcn321 | |
| parent | 724617b94bd657d71f980c5bfe2d429fc0acc27b (diff) | |
| download | linux-stable-2bf0ce3bec8b22e4bac828aeaeade15884fa0f5c.tar.gz linux-stable-2bf0ce3bec8b22e4bac828aeaeade15884fa0f5c.tar.bz2 linux-stable-2bf0ce3bec8b22e4bac828aeaeade15884fa0f5c.zip | |
drm/amd/display: Disable DC Mode Capping On DCN321
Why:
Limiting clocks to DC mode max results in some
display modes to no longer be supported
How:
Disable the path that limits the clock values
Fixes: 3b718dcaf163 ("drm/amd/display: Filter out AC mode frequencies on DC mode systems")
Reviewed-by: Martin Leung <martin.leung@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn321')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c index 28320c608aeb..ca409a441953 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c @@ -731,6 +731,7 @@ static const struct dc_debug_options debug_defaults_drv = { .fpo_vactive_min_active_margin_us = 200, .fpo_vactive_max_blank_us = 1000, .enable_legacy_fast_update = false, + .disable_dc_mode_overwrite = true, }; static struct dce_aux *dcn321_aux_engine_create( |