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authorAurabindo Pillai <aurabindo.pillai@amd.com>2023-08-23 18:15:51 -0400
committerAlex Deucher <alexander.deucher@amd.com>2023-09-11 17:16:35 -0400
commit42ab1cfed03a3248cd98ca1708f6d7520c606b27 (patch)
treef50101b7c93dd93585cc7a1f713cbebcbf62d793 /drivers/gpu/drm/amd/display/dc/dcn32
parent77ad5f6febdc17f4d06bf0b163b8612823e58d74 (diff)
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drm/amd/display: Add DCHUBBUB callback to report MALL status
[Why&How] For enabling automated testing, add a hook to DCHUBBUB interface so that mall status can be queried by userspace through debugfs. This removes dependence on requiring a userspace tool like UMR for querying status for MALL static screen IGT test. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn32')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c14
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h6
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h1
3 files changed, 19 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
index 8bfef6d095b2..88dfc907553d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
@@ -945,6 +945,17 @@ void hubbub32_force_wm_propagate_to_pipes(struct hubbub *hubbub)
DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
}
+void hubbub32_get_mall_en(struct hubbub *hubbub, unsigned int *mall_in_use)
+{
+ struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+ uint32_t prefetch_complete, mall_en;
+
+ REG_GET_2(DCHUBBUB_ARB_MALL_CNTL, MALL_IN_USE, &mall_en,
+ MALL_PREFETCH_COMPLETE, &prefetch_complete);
+
+ *mall_in_use = prefetch_complete && mall_en;
+}
+
void hubbub32_init(struct hubbub *hubbub)
{
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
@@ -995,7 +1006,8 @@ static const struct hubbub_funcs hubbub32_funcs = {
.init_crb = dcn32_init_crb,
.hubbub_read_state = hubbub2_read_state,
.force_usr_retraining_allow = hubbub32_force_usr_retraining_allow,
- .set_request_limit = hubbub32_set_request_limit
+ .set_request_limit = hubbub32_set_request_limit,
+ .get_mall_en = hubbub32_get_mall_en,
};
void hubbub32_construct(struct dcn20_hubbub *hubbub2,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
index ad33427192c6..f073839a4b6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
@@ -110,7 +110,9 @@
HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCFCLK_R_DCHUBBUB_GATE_DIS, mask_sh),\
HUBBUB_SF(DCHUBBUB_SDPIF_CFG0, SDPIF_PORT_CONTROL, mask_sh),\
HUBBUB_SF(DCHUBBUB_SDPIF_CFG1, SDPIF_MAX_NUM_OUTSTANDING, mask_sh),\
- HUBBUB_SF(DCHUBBUB_MEM_PWR_MODE_CTRL, DET_MEM_PWR_LS_MODE, mask_sh)
+ HUBBUB_SF(DCHUBBUB_MEM_PWR_MODE_CTRL, DET_MEM_PWR_LS_MODE, mask_sh),\
+ HUBBUB_SF(DCHUBBUB_ARB_MALL_CNTL, MALL_PREFETCH_COMPLETE, mask_sh),\
+ HUBBUB_SF(DCHUBBUB_ARB_MALL_CNTL, MALL_IN_USE, mask_sh)
@@ -157,4 +159,6 @@ void hubbub32_construct(struct dcn20_hubbub *hubbub2,
void hubbub32_set_request_limit(struct hubbub *hubbub, int umc_count, int words_per_umc);
+void hubbub32_get_mall_en(struct hubbub *hubbub, unsigned int *mall_in_use);
+
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
index c76de61029e0..f075982363be 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -1283,6 +1283,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B), \
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C), \
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D), \
+ SR(DCHUBBUB_ARB_MALL_CNTL), \
SR(DCN_VM_FAULT_ADDR_MSB), SR(DCN_VM_FAULT_ADDR_LSB), \
SR(DCN_VM_FAULT_CNTL), SR(DCN_VM_FAULT_STATUS), \
SR(SDPIF_REQUEST_RATE_LIMIT) \