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| author | Qingqing Zhuo <qingqing.zhuo@amd.com> | 2023-03-16 09:05:58 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-09 10:44:11 -0400 |
| commit | 25879d7b4986beba3f0d84762fe40d09fdc8b219 (patch) | |
| tree | 8c918481cd682d8ec900881801231e596a4e86a2 /drivers/gpu/drm/amd/display/dc/dml/dcn314 | |
| parent | 7e60ab4eb3e4ba2adac46d737fdbbc5732bebd58 (diff) | |
| download | linux-stable-25879d7b4986beba3f0d84762fe40d09fdc8b219.tar.gz linux-stable-25879d7b4986beba3f0d84762fe40d09fdc8b219.tar.bz2 linux-stable-25879d7b4986beba3f0d84762fe40d09fdc8b219.zip | |
drm/amd/display: Clean FPGA code in dc
[Why]
Drop dead code for Linux.
[How]
Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC
Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dml/dcn314')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c | 8 |
2 files changed, 1 insertions, 13 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c index 554152371eb5..318b9c2bc9be 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c @@ -190,8 +190,7 @@ void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p dc_assert_fp_enabled(); // Default clock levels are used for diags, which may lead to overclocking. - if (!IS_DIAG_DC(dc->ctx->dce_environment) && dc->config.use_default_clock_table == false) { - + if (dc->config.use_default_clock_table == false) { dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count; @@ -267,10 +266,7 @@ void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p dcn20_patch_bounding_box(dc, &dcn3_14_soc); - if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN314); - else - dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31_FPGA); } static bool is_dual_plane(enum surface_pixel_format format) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c index 61ba3e33bb11..b3e8dc08030c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c @@ -1520,14 +1520,6 @@ static void dml_rq_dlg_get_dlg_params( dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip); dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip); - // hack for FPGA - if (mode_lib->project == DML_PROJECT_DCN31_FPGA) { - if (disp_dlg_regs->vratio_prefetch >= (unsigned int) dml_pow(2, 22)) { - disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 22) - 1; - dml_print("vratio_prefetch exceed the max value, the register field is [21:0]\n"); - } - } - disp_dlg_regs->refcyc_per_pte_group_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13)); |