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author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2017-11-28 11:22:15 -0500 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-20 14:46:51 -0500 |
commit | 5a095c405e591fabe654d343ce4d9682e29ad3af (patch) | |
tree | 02763476ee383e0f7d4318bc061c9520fa6c4566 /drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c | |
parent | 58fc625b5e6c2ec12f8a9d635bd60f998693b2cb (diff) | |
download | linux-stable-5a095c405e591fabe654d343ce4d9682e29ad3af.tar.gz linux-stable-5a095c405e591fabe654d343ce4d9682e29ad3af.tar.bz2 linux-stable-5a095c405e591fabe654d343ce4d9682e29ad3af.zip |
drm/amd/display: clean up dcn soc params
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c index 4c31fa54af39..c109b2c34c8f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c @@ -35,35 +35,6 @@ static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum soc->writeback_latency_us = 12.0; soc->ideal_dram_bw_after_urgent_percent = 80.0; soc->max_request_size_bytes = 256; - - soc->vmin.dcfclk_mhz = 300.0; - soc->vmin.dispclk_mhz = 608.0; - soc->vmin.dppclk_mhz = 435.0; - soc->vmin.dram_bw_per_chan_gbps = 12.8; - soc->vmin.phyclk_mhz = 540.0; - soc->vmin.socclk_mhz = 208.0; - - soc->vmid.dcfclk_mhz = 600.0; - soc->vmid.dispclk_mhz = 661.0; - soc->vmid.dppclk_mhz = 661.0; - soc->vmid.dram_bw_per_chan_gbps = 12.8; - soc->vmid.phyclk_mhz = 540.0; - soc->vmid.socclk_mhz = 208.0; - - soc->vnom.dcfclk_mhz = 600.0; - soc->vnom.dispclk_mhz = 661.0; - soc->vnom.dppclk_mhz = 661.0; - soc->vnom.dram_bw_per_chan_gbps = 38.4; - soc->vnom.phyclk_mhz = 810; - soc->vnom.socclk_mhz = 208.0; - - soc->vmax.dcfclk_mhz = 600.0; - soc->vmax.dispclk_mhz = 1086.0; - soc->vmax.dppclk_mhz = 661.0; - soc->vmax.dram_bw_per_chan_gbps = 38.4; - soc->vmax.phyclk_mhz = 810.0; - soc->vmax.socclk_mhz = 208.0; - soc->downspread_percent = 0.5; soc->dram_page_open_time_ns = 50.0; soc->dram_rw_turnaround_time_ns = 17.5; |