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| author | George Shen <george.shen@amd.com> | 2023-09-22 14:26:39 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-10-09 17:00:57 -0400 |
| commit | 051d90070d4c811d7413756cc42a59f2c28e0d0f (patch) | |
| tree | 282ebc2ce5d5c92b4a5d1f0a7def2c9cb442dbf2 /drivers/gpu/drm/amd/display/dc/hwss | |
| parent | ef013f6fcd8affaae4a5bf4b51cb6244c8a2ed3f (diff) | |
| download | linux-stable-051d90070d4c811d7413756cc42a59f2c28e0d0f.tar.gz linux-stable-051d90070d4c811d7413756cc42a59f2c28e0d0f.tar.bz2 linux-stable-051d90070d4c811d7413756cc42a59f2c28e0d0f.zip | |
drm/amd/display: Refactor DPG test pattern logic for ODM cases
[Why]
Current DPG test pattern logic does not account for ODM configuration
changes after test pattern has already been programmed. For example, if
ODM2:1 is enabled after test pattern is already being output, the second
pipe is not programmed to output test pattern, causing half the screen
to be black.
[How]
Move DPG test pattern parameter calculations into separate function.
Whenever ODM pipe configuration changes, re-calculate DPG test pattern
parameters and program DPG if test pattern is currently enabled.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/hwss')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index d8c02f83b7d7..4d6493e0ccfc 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -1538,6 +1538,11 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx if (old_pipe->unbounded_req != new_pipe->unbounded_req) new_pipe->update_flags.bits.unbounded_req = 1; + + if (memcmp(&old_pipe->stream_res.test_pattern_params, + &new_pipe->stream_res.test_pattern_params, sizeof(struct test_pattern_params))) { + new_pipe->update_flags.bits.test_pattern_changed = 1; + } } static void dcn20_update_dchubp_dpp( @@ -1846,6 +1851,23 @@ static void dcn20_program_pipe( pipe_ctx->stream->abm_level); } } + + if (pipe_ctx->update_flags.bits.test_pattern_changed) { + struct output_pixel_processor *odm_opp = pipe_ctx->stream_res.opp; + struct bit_depth_reduction_params params; + + memset(¶ms, 0, sizeof(params)); + odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms); + dc->hwss.set_disp_pattern_generator(dc, + pipe_ctx, + pipe_ctx->stream_res.test_pattern_params.test_pattern, + pipe_ctx->stream_res.test_pattern_params.color_space, + pipe_ctx->stream_res.test_pattern_params.color_depth, + NULL, + pipe_ctx->stream_res.test_pattern_params.width, + pipe_ctx->stream_res.test_pattern_params.height, + pipe_ctx->stream_res.test_pattern_params.offset); + } } void dcn20_program_front_end_for_ctx( |