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| author | Alvin Lee <alvin.lee2@amd.com> | 2023-06-09 20:32:57 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-23 15:45:57 -0400 |
| commit | 12a6e62bfdcad8be49644b6dcf70c15e0e6bab6b (patch) | |
| tree | 346ee2aa608bd690f270c368baa78ba7e16d51ae /drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | |
| parent | ed83fe2abcace898fdec5c2ba0455703178ac9a3 (diff) | |
| download | linux-stable-12a6e62bfdcad8be49644b6dcf70c15e0e6bab6b.tar.gz linux-stable-12a6e62bfdcad8be49644b6dcf70c15e0e6bab6b.tar.bz2 linux-stable-12a6e62bfdcad8be49644b6dcf70c15e0e6bab6b.zip | |
drm/amd/display: Enable dc mode clock switching for DCN32x
- DC mode clock switch interface was previously only executed
for DCN303. Enable it for DCN32x so that the interface is called
correctly
- Assign function pointers for DCN32x that are used in the dc mode
interface
- Update the dc mode interface to work generically for each ASIC
- In update_clocks, make sure to consider softmax if we're in DC mode
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 6faf40fa5c69..ecb7bcc39469 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -230,6 +230,7 @@ struct clk_bw_params { unsigned int dram_channel_width_bytes; unsigned int dispclk_vco_khz; unsigned int dc_mode_softmax_memclk; + unsigned int max_memclk_mhz; struct clk_limit_table clk_table; struct wm_table wm_table; struct dummy_pstate_entry dummy_pstate_table[4]; |