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| author | Austin Zheng <austin.zheng@amd.com> | 2023-05-24 11:52:12 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-09 12:50:55 -0400 |
| commit | 3b718dcaf163d17fe907ea098c8449e0cd6bc271 (patch) | |
| tree | 30072f1c10f01cc4adca906fca11473a9ba4a0a3 /drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | |
| parent | 24e52fc20201c87912eee8f337829c036c3b0f3a (diff) | |
| download | linux-stable-3b718dcaf163d17fe907ea098c8449e0cd6bc271.tar.gz linux-stable-3b718dcaf163d17fe907ea098c8449e0cd6bc271.tar.bz2 linux-stable-3b718dcaf163d17fe907ea098c8449e0cd6bc271.zip | |
drm/amd/display: Filter out AC mode frequencies on DC mode systems
Why:
Limit maximum clock speeds to DC mode limits for DC mode systems
How:
Store DC mode limits when individual clocks are initialized and
cap the values when building the clock table
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Austin Zheng <austin.zheng@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index bef843cc32a1..6faf40fa5c69 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -233,6 +233,7 @@ struct clk_bw_params { struct clk_limit_table clk_table; struct wm_table wm_table; struct dummy_pstate_entry dummy_pstate_table[4]; + struct clk_limit_table_entry dc_mode_limit; }; /* Public interfaces */ |