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| author | Eric Yang <Eric.Yang2@amd.com> | 2019-11-10 12:08:02 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-12-05 16:28:57 -0500 |
| commit | e6d9a93c141e0bcc3a40671b2338c093d04ab14b (patch) | |
| tree | 6eb9349153236b504abe7d51305550eb566720ec /drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | |
| parent | 639dcfc6feb5c7451d1382c5d3fa1fd679eca544 (diff) | |
| download | linux-stable-e6d9a93c141e0bcc3a40671b2338c093d04ab14b.tar.gz linux-stable-e6d9a93c141e0bcc3a40671b2338c093d04ab14b.tar.bz2 linux-stable-e6d9a93c141e0bcc3a40671b2338c093d04ab14b.zip | |
drm/amd/display: fix dprefclk and ss percentage reading on RN
[Why]
Before was using HW counter value to determine the dprefclk. Which
take into account ss, but has large variation, not good enough for
generating audio dto. Also, the bios parser code to get the ss
percentage was not working.
[How]
After this change, dprefclk is hard coded, same as on RV. We don't
expect this to change on Renoir. Modified bios parser code to get
the right ss percentage.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 4aa09fe954c5..ac530c057ddd 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -191,6 +191,7 @@ struct clk_mgr { bool psr_allow_active_cache; int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes int dentist_vco_freq_khz; + struct clk_state_registers_and_bypass boot_snapshot; struct clk_bw_params *bw_params; }; |