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authorAurabindo Pillai <aurabindo.pillai@amd.com>2022-02-23 17:48:45 -0500
committerAlex Deucher <alexander.deucher@amd.com>2022-06-03 16:43:38 -0400
commitd3dfceb58de5f897640cdd424f6c2538d9514367 (patch)
tree845cec73becf5b2217e701518b68897b5928a1f7 /drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
parent235c67634230b0f9ad8c0185272fed36c892b1c4 (diff)
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drm/amd/display: Add dependant changes for DCN32/321
[Why&How] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree v2: squash in updates (Alex) Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index c1023cc84f55..b5acc6b9f3c9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -45,9 +45,10 @@ enum physymclk_clock_source {
PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.
};
-enum hdmistreamclk_source {
+enum streamclk_source {
REFCLK, // Selects REFCLK as source for hdmistreamclk.
DTBCLK0, // Selects DTBCLK0 as source for hdmistreamclk.
+ DPREFCLK, // Selects DPREFCLK as source for hdmistreamclk
};
enum dentist_dispclk_change_mode {
@@ -91,7 +92,7 @@ struct dccg_funcs {
void (*set_dpstreamclk)(
struct dccg *dccg,
- enum hdmistreamclk_source src,
+ enum streamclk_source src,
int otg_inst);
void (*enable_symclk32_se)(