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author | Alex Deucher <alexander.deucher@amd.com> | 2020-11-02 15:37:34 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2020-11-04 17:11:37 -0500 |
commit | 20f2ffe504728612d7b0c34e4f8280e34251e704 (patch) | |
tree | ab97de569be30e009ba6e5087f3f6c775167e46c /drivers/gpu/drm/amd/display/dc/inc/hw | |
parent | aeee2a48ec9239790b7c9a5c14dfb2a12554322f (diff) | |
download | linux-stable-20f2ffe504728612d7b0c34e4f8280e34251e704.tar.gz linux-stable-20f2ffe504728612d7b0c34e4f8280e34251e704.tar.bz2 linux-stable-20f2ffe504728612d7b0c34e4f8280e34251e704.zip |
drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)
Avoids confusion in configurations.
v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled
v3: rebase on latest code
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> (v1)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 26 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 19 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 6 |
11 files changed, 7 insertions, 77 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 35d1b85713b2..3a29f379d0c8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -43,7 +43,6 @@ #define DCN_MINIMUM_DISPCLK_Khz 100000 #define DCN_MINIMUM_DPPCLK_Khz 100000 -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) struct dcn3_clk_internal { int dummy; /*TODO: @@ -61,9 +60,6 @@ struct dcn3_clk_internal { */ }; -#endif - -#if defined(CONFIG_DRM_AMD_DC_DCN3_01) struct dcn301_clk_internal { int dummy; uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk @@ -79,8 +75,6 @@ struct dcn301_clk_internal { uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass }; -#endif - /* Will these bw structures be ASIC specific? */ #define MAX_NUM_DPM_LVL 8 @@ -93,12 +87,10 @@ struct clk_limit_table_entry { unsigned int fclk_mhz; unsigned int memclk_mhz; unsigned int socclk_mhz; -#ifdef CONFIG_DRM_AMD_DC_DCN3_0 unsigned int dtbclk_mhz; unsigned int dispclk_mhz; unsigned int dppclk_mhz; unsigned int phyclk_mhz; -#endif }; /* This table is contiguous */ @@ -116,8 +108,6 @@ struct wm_range_table_entry { bool valid; }; -#ifdef CONFIG_DRM_AMD_DC_DCN3_0 - struct nv_wm_range_entry { bool valid; @@ -135,7 +125,6 @@ struct nv_wm_range_entry { double sr_enter_plus_exit_time_us; } dml_input; }; -#endif struct clk_log_info { bool enabled; @@ -207,14 +196,10 @@ struct clk_bypass { * D occupied, C will be emptry. */ struct wm_table { -#ifdef CONFIG_DRM_AMD_DC_DCN3_0 union { struct nv_wm_range_entry nv_entries[WM_SET_COUNT]; -#endif - struct wm_range_table_entry entries[WM_SET_COUNT]; -#ifdef CONFIG_DRM_AMD_DC_DCN3_0 + struct wm_range_table_entry entries[WM_SET_COUNT]; }; -#endif }; struct dummy_pstate_entry { @@ -265,7 +250,6 @@ struct clk_mgr_funcs { /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link); -#ifdef CONFIG_DRM_AMD_DC_DCN3_0 /* * Send message to PMFW to set hard min memclk frequency * When current_mode = false, set DPM0 @@ -278,10 +262,8 @@ struct clk_mgr_funcs { /* Get current memclk states from PMFW, update relevant structures */ void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr); -#endif }; -#ifdef CONFIG_DRM_AMD_DC_DCN3_01 struct dpm_clocks; struct wartermarks; @@ -290,24 +272,18 @@ struct smu_watermark_set { union large_integer mc_address; }; -#endif - struct clk_mgr { struct dc_context *ctx; struct clk_mgr_funcs *funcs; struct dc_clocks clks; bool psr_allow_active_cache; -#ifdef CONFIG_DRM_AMD_DC_DCN3_0 bool force_smu_not_present; -#endif int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes int dentist_vco_freq_khz; struct clk_state_registers_and_bypass boot_snapshot; struct clk_bw_params *bw_params; struct pp_smu_wm_range_sets ranges; -#ifdef CONFIG_DRM_AMD_DC_DCN3_01 struct smu_watermark_set smu_wm_set; -#endif }; /* forward declarations */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index 949b61351ede..ffd37696b6b9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -107,11 +107,9 @@ enum dentist_divider_range { CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \ CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0) -#ifdef CONFIG_DRM_AMD_DC_DCN3_0 // TODO: #define CLK_REG_LIST_DCN3() \ SR(DENTIST_DISPCLK_CNTL) -#endif #define CLK_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -185,10 +183,9 @@ struct clk_mgr_registers { uint32_t CLK3_CLK2_DFS_CNTL; uint32_t CLK3_CLK_PLL_REQ; -#ifdef CONFIG_DRM_AMD_DC_DCN3_0 uint32_t CLK0_CLK2_DFS_CNTL; uint32_t CLK0_CLK_PLL_REQ; -#endif + uint32_t MP1_SMN_C2PMSG_67; uint32_t MP1_SMN_C2PMSG_83; uint32_t MP1_SMN_C2PMSG_91; @@ -285,12 +282,10 @@ struct clk_mgr_internal { bool periodic_retraining_disabled; unsigned int cur_phyclk_req_table[MAX_PIPES * 2]; -#ifdef CONFIG_DRM_AMD_DC_DCN3_0 bool smu_present; void *wm_range_table; long long wm_range_table_addr; -#endif }; struct clk_mgr_internal_funcs { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h index bf4d6190dd00..5425e92efcb8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h @@ -31,9 +31,7 @@ enum dcc_control { dcc_control__256_256_xxx, dcc_control__128_128_xxx, dcc_control__256_64_64, -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) dcc_control__256_128_128, -#endif }; enum segment_order { @@ -65,9 +63,7 @@ enum dcn_hubbub_page_table_depth { enum dcn_hubbub_page_table_block_size { DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0, DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4, -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) DCN_PAGE_TABLE_BLOCK_SIZE_32KB = 3 -#endif }; struct dcn_hubbub_phys_addr_config { @@ -152,12 +148,10 @@ struct hubbub_funcs { void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub); void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub); -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow); void (*init_watermarks)(struct hubbub *hubbub); -#endif }; struct hubbub { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index 0491720c5fe9..6751186f6f90 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -121,13 +121,11 @@ struct CM_bias_params { }; struct dpp_funcs { -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) bool (*dpp_program_gamcor_lut)( struct dpp *dpp_base, const struct pwl_params *params); void (*dpp_set_pre_degam)(struct dpp *dpp_base, enum dc_transfer_func_predefined tr); -#endif void (*dpp_program_cm_dealpha)(struct dpp *dpp_base, uint32_t enable, uint32_t additive_blending); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h index 3407e5da5534..ec28cb9c3a8e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h @@ -72,14 +72,14 @@ enum wbscl_coef_filter_type_sel { }; -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) enum dwb_boundary_mode { DWBSCL_BOUNDARY_MODE_EDGE = 0, DWBSCL_BOUNDARY_MODE_BLACK = 1 }; #endif -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) enum dwb_output_csc_mode { DWB_OUTPUT_CSC_DISABLE = 0, DWB_OUTPUT_CSC_COEF_A = 1, @@ -209,7 +209,7 @@ struct dwbc_funcs { struct dwb_warmup_params *warmup_params); -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) void (*dwb_program_output_csc)( struct dwbc *dwbc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index 0dbd5a55de33..315e3061c592 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -48,10 +48,8 @@ enum cursor_lines_per_chunk { enum hubp_ind_block_size { hubp_ind_block_unconstrained = 0, hubp_ind_block_64b, -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) hubp_ind_block_128b, hubp_ind_block_64b_no_128bcl, -#endif }; struct hubp { @@ -187,11 +185,9 @@ struct hubp_funcs { struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr); -#if defined(CONFIG_DRM_AMD_DC_DCN3_01) void (*set_unbounded_requesting)( struct hubp *hubp, bool enable); -#endif }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index f62ccf242f56..a3a27c16aa2f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -150,14 +150,12 @@ enum ipp_degamma_mode { IPP_DEGAMMA_MODE_USER_PWL }; -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) enum gamcor_mode { GAMCOR_MODE_BYPASS, GAMCOR_MODE_RESERVED_1, GAMCOR_MODE_USER_PWL, GAMCOR_MODE_RESERVED_3 }; -#endif enum ipp_output_format { IPP_OUTPUT_FORMAT_12_BIT_FIX, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h index aeab7fd782b8..15cb782f129b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h @@ -43,9 +43,7 @@ struct mcif_arb_params { unsigned int arbitration_slice; unsigned int slice_lines; unsigned int max_scaled_time; -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) unsigned int dram_speed_change_duration; -#endif }; struct mcif_irq_params { @@ -75,11 +73,9 @@ struct mcif_wb { struct mcif_wb_funcs { -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) void (*warmup_mcif)( struct mcif_wb *mcif_wb, struct mcif_warmup_params *params); -#endif void (*enable_mcif)(struct mcif_wb *mcif_wb); void (*disable_mcif)(struct mcif_wb *mcif_wb); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index b2892eab5e02..879f502ae530 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -32,11 +32,7 @@ #define MAX_MPCC 6 #define MAX_OPP 6 -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) #define MAX_DWB 2 -#else -#define MAX_DWB 1 -#endif enum mpc_output_csc_mode { MPC_OUTPUT_CSC_DISABLE = 0, @@ -77,12 +73,11 @@ struct mpcc_blnd_cfg { int bottom_outside_gain; }; -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) struct mpc_grph_gamut_adjustment { struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE]; enum graphics_gamut_adjust_type gamut_adjust_type; }; -#endif + struct mpcc_sm_cfg { bool enable; /* 0-single plane,2-row subsampling,4-column subsampling,6-checkboard subsampling */ @@ -106,13 +101,12 @@ struct mpc_denorm_clamp { int clamp_min_b_cb; }; -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) struct mpc_dwb_flow_control { int flow_ctrl_mode; int flow_ctrl_cnt0; int flow_ctrl_cnt1; }; -#endif + /* * MPCC connection and blending configuration for a single MPCC instance. * This struct is used as a node in an MPC tree. @@ -123,9 +117,7 @@ struct mpcc { struct mpcc *mpcc_bot; /* pointer to bottom layer MPCC. NULL when not connected */ struct mpcc_blnd_cfg blnd_cfg; /* The blending configuration for this MPCC */ struct mpcc_sm_cfg sm_cfg; /* stereo mix setting for this MPCC */ -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) bool shared_bottom; /* TRUE if MPCC output to both OPP and DWB endpoints, else FALSE */ -#endif }; /* @@ -247,7 +239,6 @@ struct mpc_funcs { int opp_id, bool lock); -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) /* * Add DPP into 'secondary' MPC tree based on specified blending position. * Only used for planes that are part of blending chain for DWB output @@ -290,7 +281,6 @@ struct mpc_funcs { struct mpcc* (*get_mpcc_for_dpp_from_secondary)( struct mpc_tree *tree, int dpp_id); -#endif struct mpcc* (*get_mpcc_for_dpp)( struct mpc_tree *tree, int dpp_id); @@ -330,7 +320,6 @@ struct mpc_funcs { struct mpc *mpc, int mpcc_id, bool power_on); -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) void (*set_dwb_mux)( struct mpc *mpc, int dwb_id, @@ -350,9 +339,7 @@ struct mpc_funcs { bool enable, bool rate_2x_mode, struct mpc_dwb_flow_control *flow_control); -#endif -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) void (*set_gamut_remap)( struct mpc *mpc, int mpcc_id, @@ -372,8 +359,6 @@ struct mpc_funcs { int (*release_rmu)(struct mpc *mpc, int mpcc_id); -#endif - }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index 0184cefb083b..47c7e4c3a51b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -104,10 +104,8 @@ struct stream_encoder { struct dc_bios *bp; enum engine_id id; uint32_t stream_enc_inst; -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) struct vpg *vpg; struct afmt *afmt; -#endif }; struct enc_state { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 084432132b16..12d5718caea8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -98,19 +98,15 @@ enum crc_selection { INTERSECT_WINDOW_NOT_A_NOT_B, }; -#ifdef CONFIG_DRM_AMD_DC_DCN3_0 enum otg_out_mux_dest { OUT_MUX_DIO = 0, }; -#endif enum h_timing_div_mode { H_TIMING_NO_DIV, H_TIMING_DIV_BY2, -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) H_TIMING_RESERVED, H_TIMING_DIV_BY4, -#endif }; struct crc_params { @@ -288,7 +284,6 @@ struct timing_generator_funcs { void (*set_gsl_source_select)(struct timing_generator *optc, int group_idx, uint32_t gsl_ready_signal); -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest); void (*set_vrr_m_const)(struct timing_generator *optc, double vtotal_avg); @@ -296,7 +291,6 @@ struct timing_generator_funcs { uint32_t window_start, uint32_t window_end); void (*set_vtotal_change_limit)(struct timing_generator *optc, uint32_t limit); -#endif }; #endif |