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| author | Wenjing Liu <wenjing.liu@amd.com> | 2024-04-25 12:13:24 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-05-13 15:46:55 -0400 |
| commit | f9d48a88eba547d87d8ea7bfd25abd1836cdf06a (patch) | |
| tree | f6132f1828d08eca7106892aea1762c13b5fbfeb /drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c | |
| parent | d5192c15fa6a8bb594e9ea23561019f77565a227 (diff) | |
| download | linux-stable-f9d48a88eba547d87d8ea7bfd25abd1836cdf06a.tar.gz linux-stable-f9d48a88eba547d87d8ea7bfd25abd1836cdf06a.tar.bz2 linux-stable-f9d48a88eba547d87d8ea7bfd25abd1836cdf06a.zip | |
drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split
[WHY]
Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODM
pipesplit is used, pixels on the left edge of ODM slices need one extra
pixel from the right edge of the previous slice to calculate the correct
chroma value.
Without this change, the chroma value is slightly different than
expected. This is usually imperceptible visually, but it impacts test
pattern CRCs for compliance test automation.
[HOW]
Update logic to use the register for adding extra left edge pixel for
YCbCr422/420 ODM cases.
Reviewed-by: George Shen <george.shen@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c index cf8da22492dc..7c9faa507ec2 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c @@ -55,12 +55,11 @@ * Return: void. */ static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, - struct dc_crtc_timing *timing) + int segment_width, int last_segment_width) { struct optc *optc1 = DCN10TG_FROM_TG(optc); uint32_t memory_mask = 0; - int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; - int mpcc_hactive = h_active / opp_cnt; + int h_active = segment_width * opp_cnt; /* Each memory instance is 2048x(314x2) bits to support half line of 4096 */ int odm_mem_count = (h_active + 2047) / 2048; @@ -103,7 +102,7 @@ static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, i } REG_UPDATE(OPTC_WIDTH_CONTROL, - OPTC_SEGMENT_WIDTH, mpcc_hactive); + OPTC_SEGMENT_WIDTH, segment_width); REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); optc1->opp_count = opp_cnt; |