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| author | Wenjing Liu <wenjing.liu@amd.com> | 2023-11-02 14:59:13 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-11-29 16:48:59 -0500 |
| commit | cfab803884f426b36b58dbe1f86f99742767c208 (patch) | |
| tree | a2b47b8547726268baa4cd5fa8bd9ad9747c9a2c /drivers/gpu/drm/amd/display/dc/resource/dcn321 | |
| parent | 2e9b152325f649923b9324fa8ea5f1a5289145bb (diff) | |
| download | linux-stable-cfab803884f426b36b58dbe1f86f99742767c208.tar.gz linux-stable-cfab803884f426b36b58dbe1f86f99742767c208.tar.bz2 linux-stable-cfab803884f426b36b58dbe1f86f99742767c208.zip | |
drm/amd/display: update pixel clock params after stream slice count change in context
[why]
When ODM slice count is changed, otg master pipe's pixel clock params is
no longer valid as the value is dependent on ODM slice count.
Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/resource/dcn321')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index bedb70b98162..12986fe0b289 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -1609,6 +1609,7 @@ static struct resource_funcs dcn321_res_pool_funcs = { .retain_phantom_pipes = dcn32_retain_phantom_pipes, .save_mall_state = dcn32_save_mall_state, .restore_mall_state = dcn32_restore_mall_state, + .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, }; static uint32_t read_pipe_fuses(struct dc_context *ctx) |