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author | Alvin Lee <alvin.lee2@amd.com> | 2023-11-09 10:50:30 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2023-11-29 16:49:00 -0500 |
commit | 8f3656ce65d6d550247a85fdb5c54a5b65cc2252 (patch) | |
tree | 191496fff33a7f7aa21f30e2862a365a2ebf3d6d /drivers/gpu/drm/amd/display/dc/resource/dcn32 | |
parent | 5f2a404cbccec0c8d6635f0997cea2ac226d25d4 (diff) | |
download | linux-stable-8f3656ce65d6d550247a85fdb5c54a5b65cc2252.tar.gz linux-stable-8f3656ce65d6d550247a85fdb5c54a5b65cc2252.tar.bz2 linux-stable-8f3656ce65d6d550247a85fdb5c54a5b65cc2252.zip |
drm/amd/display: Enable SubVP on 1080p60 displays
[Description]
- Previously SubVP would never be selected on 1080p60 displays because
it has too much vactive margin. However, implement a change to allow
it like how 1440p60 is allowed.
- Add a new struct such that we have a list of allowed modes for
enabling subvp with vactive margin (currently 1080p60 and 1440p60)
- Also ensure to block drr + vblank cases to prevent unexpected
enablement of new display configs
- Update SW cursor fallback for these new potential cases as well
Reviewed-by: Samson Tam <samson.tam@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/resource/dcn32')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h index b931008114c9..b2f20e6cfb38 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h @@ -39,6 +39,7 @@ #define DCN3_2_MBLK_HEIGHT_8BPE 64 #define DCN3_2_DCFCLK_DS_INIT_KHZ 10000 // Choose 10Mhz for init DCFCLK DS freq #define SUBVP_HIGH_REFRESH_LIST_LEN 4 +#define SUBVP_ACTIVE_MARGIN_LIST_LEN 2 #define DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ 1800 #define DCN3_2_VMIN_DISPCLK_HZ 717000000 @@ -57,6 +58,15 @@ struct subvp_high_refresh_list { } res[SUBVP_HIGH_REFRESH_LIST_LEN]; }; +struct subvp_active_margin_list { + int min_refresh; + int max_refresh; + struct { + int width; + int height; + } res[SUBVP_ACTIVE_MARGIN_LIST_LEN]; +}; + struct dcn32_resource_pool { struct resource_pool base; }; |