diff options
author | Sung Lee <sung.lee@amd.com> | 2020-01-23 15:31:43 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2020-02-06 15:04:37 -0500 |
commit | c788739b8807a54b4f445f2c2854d37b61db49c2 (patch) | |
tree | c37d09ca8c0d29266133660779b26f4b36347b78 /drivers/gpu/drm/amd/display/dc | |
parent | 32caf906187dee2f895a469f7d9f0a8e6e43e287 (diff) | |
download | linux-stable-c788739b8807a54b4f445f2c2854d37b61db49c2.tar.gz linux-stable-c788739b8807a54b4f445f2c2854d37b61db49c2.tar.bz2 linux-stable-c788739b8807a54b4f445f2c2854d37b61db49c2.zip |
drm/amd/display: Add wm ranges to clk_mgr
[WHY & HOW]
Having watermark ranges saved inside clk_mgr to be
available for debug at all times would be useful.
Add it to the clk_mgr_internal struct for reference.
Only populated for Renoir, unused for other asics.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 2 |
2 files changed, 4 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index 034a5852a416..8ecb98c29eb9 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -459,16 +459,15 @@ void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_ra static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base) { struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug; - struct pp_smu_wm_range_sets ranges = {0}; struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu; if (!debug->disable_pplib_wm_range) { - build_watermark_ranges(clk_mgr_base->bw_params, &ranges); + build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges); /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ if (pp_smu && pp_smu->rn_funcs.set_wm_ranges) - pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges); + pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges); } } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index ac530c057ddd..ce65678c03b2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -27,6 +27,7 @@ #define __DAL_CLK_MGR_H__ #include "dc.h" +#include "dm_pp_smu.h" #define DCN_MINIMUM_DISPCLK_Khz 100000 #define DCN_MINIMUM_DPPCLK_Khz 100000 @@ -193,6 +194,7 @@ struct clk_mgr { int dentist_vco_freq_khz; struct clk_state_registers_and_bypass boot_snapshot; struct clk_bw_params *bw_params; + struct pp_smu_wm_range_sets ranges; }; /* forward declarations */ |