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author | Asad Kamal <asad.kamal@amd.com> | 2023-09-27 21:05:37 +0800 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2023-10-13 10:59:02 -0400 |
commit | 011d99ee71d9aefc7ddd395d3337674c03ae2748 (patch) | |
tree | 49e5cd02abd1b4e19d403ae24ce53a4d7267df38 /drivers/gpu/drm/amd/include | |
parent | 79b049064afcd34b822ab4bda6be404fe5a09c6f (diff) | |
download | linux-stable-011d99ee71d9aefc7ddd395d3337674c03ae2748.tar.gz linux-stable-011d99ee71d9aefc7ddd395d3337674c03ae2748.tar.bz2 linux-stable-011d99ee71d9aefc7ddd395d3337674c03ae2748.zip |
drm/amd/pm: Add gpu_metrics_v1_4
Add new gpu_metrics_v1_4 to acquire XGMI data transfer,
pcie bandwidth & Clock lock status
v2:
Add pcie error counter to gpu metric table v1_4
Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
-rw-r--r-- | drivers/gpu/drm/amd/include/kgd_pp_interface.h | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index e0bb6d39f0c3..eeb547d79eac 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -313,6 +313,10 @@ enum pp_xgmi_plpd_mode { #define XGMI_MODE_PSTATE_D0 1 #define NUM_HBM_INSTANCES 4 +#define NUM_XGMI_LINKS 8 +#define MAX_GFX_CLKS 8 +#define MAX_CLKS 4 +#define NUM_VCN 4 struct seq_file; enum amd_pp_clock_type; @@ -696,6 +700,78 @@ struct gpu_metrics_v1_3 { uint64_t indep_throttle_status; }; +struct gpu_metrics_v1_4 { + struct metrics_table_header common_header; + + /* Temperature (Celsius) */ + uint16_t temperature_hotspot; + uint16_t temperature_mem; + uint16_t temperature_vrsoc; + + /* Power (Watts) */ + uint16_t curr_socket_power; + + /* Utilization (%) */ + uint16_t average_gfx_activity; + uint16_t average_umc_activity; // memory controller + uint16_t vcn_activity[NUM_VCN]; + + /* Energy (15.259uJ (2^-16) units) */ + uint64_t energy_accumulator; + + /* Driver attached timestamp (in ns) */ + uint64_t system_clock_counter; + + /* Throttle status */ + uint32_t throttle_status; + + /* Clock Lock Status. Each bit corresponds to clock instance */ + uint32_t gfxclk_lock_status; + + /* Link width (number of lanes) and speed (in 0.1 GT/s) */ + uint16_t pcie_link_width; + uint16_t pcie_link_speed; + + /* XGMI bus width and bitrate (in Gbps) */ + uint16_t xgmi_link_width; + uint16_t xgmi_link_speed; + + /* Utilization Accumulated (%) */ + uint32_t gfx_activity_acc; + uint32_t mem_activity_acc; + + /*PCIE accumulated bandwidth (GB/sec) */ + uint64_t pcie_bandwidth_acc; + + /*PCIE instantaneous bandwidth (GB/sec) */ + uint64_t pcie_bandwidth_inst; + + /* PCIE L0 to recovery state transition accumulated count */ + uint64_t pcie_l0_to_recov_count_acc; + + /* PCIE replay accumulated count */ + uint64_t pcie_replay_count_acc; + + /* PCIE replay rollover accumulated count */ + uint64_t pcie_replay_rover_count_acc; + + /* XGMI accumulated data transfer size(KiloBytes) */ + uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; + uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; + + /* PMFW attached timestamp (10ns resolution) */ + uint64_t firmware_timestamp; + + /* Current clocks (Mhz) */ + uint16_t current_gfxclk[MAX_GFX_CLKS]; + uint16_t current_socclk[MAX_CLKS]; + uint16_t current_vclk0[MAX_CLKS]; + uint16_t current_dclk0[MAX_CLKS]; + uint16_t current_uclk; + + uint16_t padding; +}; + /* * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. * Use gpu_metrics_v2_1 or later instead. |