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| author | Horace Chen <horace.chen@amd.com> | 2021-02-25 15:22:51 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-05 15:10:35 -0500 |
| commit | 4215a11923362ec53e85dfe25160beeebf41fd2c (patch) | |
| tree | 28109210c42d729b123307bcf2ce3d085758a348 /drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | |
| parent | 152bb95c38c3460f077c8e97f6576b2656a4d974 (diff) | |
| download | linux-stable-4215a11923362ec53e85dfe25160beeebf41fd2c.tar.gz linux-stable-4215a11923362ec53e85dfe25160beeebf41fd2c.tar.bz2 linux-stable-4215a11923362ec53e85dfe25160beeebf41fd2c.zip | |
drm/amdgpu: enable one vf mode on sienna cichlid vf
sienna cichlid needs one vf mode which allows vf to set and get
clock status from guest vm. So now expose the required interface
and allow some smu request on VF mode. Also since this asic blocked
direct MMIO access, use KIQ to send SMU request under sriov vf.
OD use same command as getting pp table which is not allowed for
sienna cichlid, so remove OD feature under sriov vf.
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Monk Liu<monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c')
| -rw-r--r-- | drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index f5d9590f2178..3d0a165bf563 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -653,10 +653,12 @@ static int smu_late_init(void *handle) return ret; } - ret = smu_set_default_od_settings(smu); - if (ret) { - dev_err(adev->dev, "Failed to setup default OD settings!\n"); - return ret; + if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { + ret = smu_set_default_od_settings(smu); + if (ret) { + dev_err(adev->dev, "Failed to setup default OD settings!\n"); + return ret; + } } ret = smu_populate_umd_state_clk(smu); |