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| author | Kevin Wang <kevin1.wang@amd.com> | 2020-10-21 00:09:36 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-23 22:54:24 -0400 |
| commit | c05d1c401572ac63d704183b19db2ce746961412 (patch) | |
| tree | 94bd7270da9ab0e6ec8ecf3ad794bcae557925a0 /drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | |
| parent | 465c437aac49c7d435c4447a15249f4d5623530c (diff) | |
| download | linux-stable-c05d1c401572ac63d704183b19db2ce746961412.tar.gz linux-stable-c05d1c401572ac63d704183b19db2ce746961412.tar.bz2 linux-stable-c05d1c401572ac63d704183b19db2ce746961412.zip | |
drm/amd/swsmu: add aldebaran smu13 ip support (v3)
Add initial swSMU support.
v1: add smu13 ip support for aldebaran asic (Kevin/Kenneth)
v2: switch to thm/mp v13_0 ip headers (Hawking)
v3: squash in updates (Alex)
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c')
| -rw-r--r-- | drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 502e1b926a06..ffddee897d05 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -34,6 +34,7 @@ #include "sienna_cichlid_ppt.h" #include "renoir_ppt.h" #include "vangogh_ppt.h" +#include "aldebaran_ppt.h" #include "amd_pcie.h" /* @@ -555,6 +556,11 @@ static int smu_set_funcs(struct amdgpu_device *adev) case CHIP_DIMGREY_CAVEFISH: sienna_cichlid_set_ppt_funcs(smu); break; + case CHIP_ALDEBARAN: + aldebaran_set_ppt_funcs(smu); + /* OD is not supported on Aldebaran */ + smu->od_enabled = false; + break; case CHIP_RENOIR: renoir_set_ppt_funcs(smu); break; @@ -2071,6 +2077,15 @@ const struct amdgpu_ip_block_version smu_v12_0_ip_block = .funcs = &smu_ip_funcs, }; +const struct amdgpu_ip_block_version smu_v13_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_SMC, + .major = 13, + .minor = 0, + .rev = 0, + .funcs = &smu_ip_funcs, +}; + int smu_load_microcode(struct smu_context *smu) { int ret = 0; |