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| author | Yang Wang <kevinyang.wang@amd.com> | 2023-10-24 14:00:39 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-11-09 17:01:20 -0500 |
| commit | bf13da6ae1a0097cf2ff4fba1e3236aaa3fa3a7a (patch) | |
| tree | de753196b14bec2dad8e7d3a5a4e3b44cb0d61a7 /drivers/gpu/drm/amd/pm/swsmu | |
| parent | bc3c566071c8504f5d7c73a4171ead394f097639 (diff) | |
| download | linux-stable-bf13da6ae1a0097cf2ff4fba1e3236aaa3fa3a7a.tar.gz linux-stable-bf13da6ae1a0097cf2ff4fba1e3236aaa3fa3a7a.tar.bz2 linux-stable-bf13da6ae1a0097cf2ff4fba1e3236aaa3fa3a7a.zip | |
drm/amdgpu: correct smu v13.0.6 umc ras error check
correct smu v13.0.0 umc ras error check
Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/pm/swsmu')
| -rw-r--r-- | drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 83e1228e6eee..a6b57a5d0c77 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -48,6 +48,7 @@ #include "smu_cmn.h" #include "mp/mp_13_0_6_offset.h" #include "mp/mp_13_0_6_sh_mask.h" +#include "umc_v12_0.h" #undef MP1_Public #undef smnMP1_FIRMWARE_FLAGS @@ -2481,7 +2482,7 @@ static int mca_decode_mca_ipid(struct amdgpu_device *adev, enum amdgpu_mca_error return 0; } -static int mca_normal_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev, +static int mca_umc_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev, enum amdgpu_mca_error_type type, int idx, uint32_t *count) { uint64_t status0; @@ -2491,10 +2492,15 @@ static int mca_normal_mca_get_err_count(const struct mca_ras_info *mca_ras, stru if (ret) return ret; - if (REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) - *count = 1; - else + if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) { *count = 0; + return 0; + } + + if (type == AMDGPU_MCA_ERROR_TYPE_UE && umc_v12_0_is_uncorrectable_error(status0)) + *count = 1; + else if (type == AMDGPU_MCA_ERROR_TYPE_CE && umc_v12_0_is_correctable_error(status0)) + *count = 1; return 0; } @@ -2608,7 +2614,7 @@ static const struct mca_ras_info mca_ras_table[] = { { .blkid = AMDGPU_RAS_BLOCK__UMC, .ip = AMDGPU_MCA_IP_UMC, - .get_err_count = mca_normal_mca_get_err_count, + .get_err_count = mca_umc_mca_get_err_count, }, { .blkid = AMDGPU_RAS_BLOCK__GFX, .ip = AMDGPU_MCA_IP_MP5, |