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| author | Eric Huang <JinHuiEric.Huang@amd.com> | 2016-02-09 16:26:00 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2016-05-04 20:26:42 -0400 |
| commit | 03e3905f21c03beea8f68f2c4cf94cf36e53b160 (patch) | |
| tree | 4f9ac2d253cd9fa3314f69c6dff7aef0b69dd459 /drivers/gpu/drm/amd/powerplay/amd_powerplay.c | |
| parent | e85c7d664dbf2324990ceb3cd47eaaa4ea8f61fc (diff) | |
| download | linux-stable-03e3905f21c03beea8f68f2c4cf94cf36e53b160.tar.gz linux-stable-03e3905f21c03beea8f68f2c4cf94cf36e53b160.tar.bz2 linux-stable-03e3905f21c03beea8f68f2c4cf94cf36e53b160.zip | |
drm/amd/powerplay: add all blocks clockgating support through SMU/powerplay
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/amd_powerplay.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 9d2290044708..9c742e0a9d35 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -180,6 +180,87 @@ static void pp_print_status(void *handle) static int pp_set_clockgating_state(void *handle, enum amd_clockgating_state state) { + struct pp_hwmgr *hwmgr; + uint32_t msg_id, pp_state; + + if (handle == NULL) + return -EINVAL; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || + hwmgr->hwmgr_func->update_clock_gatings == NULL) + return -EINVAL; + + if (state == AMD_CG_STATE_UNGATE) + pp_state = 0; + else + pp_state = PP_STATE_CG | PP_STATE_LS; + + /* Enable/disable GFX blocks clock gating through SMU */ + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, + PP_BLOCK_GFX_CG, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, + PP_BLOCK_GFX_3D, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, + PP_BLOCK_GFX_RLC, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, + PP_BLOCK_GFX_CP, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, + PP_BLOCK_GFX_MG, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + + /* Enable/disable System blocks clock gating through SMU */ + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, + PP_BLOCK_SYS_BIF, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, + PP_BLOCK_SYS_BIF, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, + PP_BLOCK_SYS_MC, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, + PP_BLOCK_SYS_ROM, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, + PP_BLOCK_SYS_DRM, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, + PP_BLOCK_SYS_HDP, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, + PP_BLOCK_SYS_SDMA, + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, + pp_state); + hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); + return 0; } |