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author | Evan Quan <evan.quan@amd.com> | 2020-01-03 14:24:56 +0800 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2020-01-07 12:01:48 -0500 |
commit | e0aa4a92f76b8b1a361f6ae6b0a51854e3113416 (patch) | |
tree | 4b35bb9b0d753deac3c253420fc6e967625e4b9f /drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | |
parent | 29a45960647b243af5f2aa73fd7a822ef3db33eb (diff) | |
download | linux-stable-e0aa4a92f76b8b1a361f6ae6b0a51854e3113416.tar.gz linux-stable-e0aa4a92f76b8b1a361f6ae6b0a51854e3113416.tar.bz2 linux-stable-e0aa4a92f76b8b1a361f6ae6b0a51854e3113416.zip |
drm/amd/powerplay: issue proper hdp flush for table transferring
Guard the content consistence between the view of GPU and CPU
during the table transferring.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c index 39427ca32a15..715564009089 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c @@ -58,7 +58,7 @@ static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr, priv->smu_tables.entry[table_id].table_id); /* flush hdp cache */ - adev->nbio.funcs->hdp_flush(adev, NULL); + amdgpu_asic_flush_hdp(adev, NULL); memcpy(table, priv->smu_tables.entry[table_id].table, priv->smu_tables.entry[table_id].size); @@ -70,6 +70,7 @@ static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr, uint8_t *table, int16_t table_id) { struct vega10_smumgr *priv = hwmgr->smu_backend; + struct amdgpu_device *adev = hwmgr->adev; /* under sriov, vbios or hypervisor driver * has already copy table to smc so here only skip it @@ -87,6 +88,8 @@ static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr, memcpy(priv->smu_tables.entry[table_id].table, table, priv->smu_tables.entry[table_id].size); + amdgpu_asic_flush_hdp(adev, NULL); + smu9_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDriverDramAddrHigh, upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)); |