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author | Evan Quan <evan.quan@amd.com> | 2019-07-11 10:23:17 +0800 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2019-07-18 14:18:07 -0500 |
commit | 7e01a2ec96bf8a149c5e83d0352cf6ea286275cf (patch) | |
tree | 1c3056f2bb447a3137b5af65cc0f9cdccd81721a /drivers/gpu/drm/amd/powerplay/vega20_ppt.c | |
parent | a08a4dae7a11d6665c8d2a49a2c01e8a71a18955 (diff) | |
download | linux-stable-7e01a2ec96bf8a149c5e83d0352cf6ea286275cf.tar.gz linux-stable-7e01a2ec96bf8a149c5e83d0352cf6ea286275cf.tar.bz2 linux-stable-7e01a2ec96bf8a149c5e83d0352cf6ea286275cf.zip |
drm/amd/powerplay: correct SW SMU valid mapping check
Current implementation is not actually able to detect
invalid message/table/workload mapping.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/vega20_ppt.c')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 67 |
1 files changed, 37 insertions, 30 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c index bb9bb09cfc7a..af54fee0aed2 100644 --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c @@ -47,7 +47,7 @@ #define CTF_OFFSET_HBM 5 #define MSG_MAP(msg) \ - [SMU_MSG_##msg] = PPSMC_MSG_##msg + [SMU_MSG_##msg] = {1, PPSMC_MSG_##msg} #define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \ FEATURE_DPM_GFXCLK_MASK | \ @@ -59,7 +59,7 @@ FEATURE_DPM_LINK_MASK | \ FEATURE_DPM_DCEFCLK_MASK) -static int vega20_message_map[SMU_MSG_MAX_COUNT] = { +static struct smu_11_0_cmn2aisc_mapping vega20_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage), MSG_MAP(GetSmuVersion), MSG_MAP(GetDriverIfVersion), @@ -145,7 +145,7 @@ static int vega20_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(GetAVFSVoltageByDpm), }; -static int vega20_clk_map[SMU_CLK_COUNT] = { +static struct smu_11_0_cmn2aisc_mapping vega20_clk_map[SMU_CLK_COUNT] = { CLK_MAP(GFXCLK, PPCLK_GFXCLK), CLK_MAP(VCLK, PPCLK_VCLK), CLK_MAP(DCLK, PPCLK_DCLK), @@ -159,7 +159,7 @@ static int vega20_clk_map[SMU_CLK_COUNT] = { CLK_MAP(FCLK, PPCLK_FCLK), }; -static int vega20_feature_mask_map[SMU_FEATURE_COUNT] = { +static struct smu_11_0_cmn2aisc_mapping vega20_feature_mask_map[SMU_FEATURE_COUNT] = { FEA_MAP(DPM_PREFETCHER), FEA_MAP(DPM_GFXCLK), FEA_MAP(DPM_UCLK), @@ -195,7 +195,7 @@ static int vega20_feature_mask_map[SMU_FEATURE_COUNT] = { FEA_MAP(XGMI), }; -static int vega20_table_map[SMU_TABLE_COUNT] = { +static struct smu_11_0_cmn2aisc_mapping vega20_table_map[SMU_TABLE_COUNT] = { TAB_MAP(PPTABLE), TAB_MAP(WATERMARKS), TAB_MAP(AVFS), @@ -208,12 +208,12 @@ static int vega20_table_map[SMU_TABLE_COUNT] = { TAB_MAP(OVERDRIVE), }; -static int vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { +static struct smu_11_0_cmn2aisc_mapping vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { PWR_MAP(AC), PWR_MAP(DC), }; -static int vega20_workload_map[] = { +static struct smu_11_0_cmn2aisc_mapping vega20_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_DEFAULT_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), @@ -225,79 +225,86 @@ static int vega20_workload_map[] = { static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index) { - int val; + struct smu_11_0_cmn2aisc_mapping mapping; + if (index >= SMU_TABLE_COUNT) return -EINVAL; - val = vega20_table_map[index]; - if (val >= TABLE_COUNT) + mapping = vega20_table_map[index]; + if (!(mapping.valid_mapping)) return -EINVAL; - return val; + return mapping.map_to; } static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index) { - int val; + struct smu_11_0_cmn2aisc_mapping mapping; + if (index >= SMU_POWER_SOURCE_COUNT) return -EINVAL; - val = vega20_pwr_src_map[index]; - if (val >= POWER_SOURCE_COUNT) + mapping = vega20_pwr_src_map[index]; + if (!(mapping.valid_mapping)) return -EINVAL; - return val; + return mapping.map_to; } static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index) { - int val; + struct smu_11_0_cmn2aisc_mapping mapping; + if (index >= SMU_FEATURE_COUNT) return -EINVAL; - val = vega20_feature_mask_map[index]; - if (val > 64) + mapping = vega20_feature_mask_map[index]; + if (!(mapping.valid_mapping)) return -EINVAL; - return val; + return mapping.map_to; } static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index) { - int val; + struct smu_11_0_cmn2aisc_mapping mapping; + if (index >= SMU_CLK_COUNT) return -EINVAL; - val = vega20_clk_map[index]; - if (val >= PPCLK_COUNT) + mapping = vega20_clk_map[index]; + if (!(mapping.valid_mapping)) return -EINVAL; - return val; + return mapping.map_to; } static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index) { - int val; + struct smu_11_0_cmn2aisc_mapping mapping; if (index >= SMU_MSG_MAX_COUNT) return -EINVAL; - val = vega20_message_map[index]; - if (val > PPSMC_Message_Count) + mapping = vega20_message_map[index]; + if (!(mapping.valid_mapping)) return -EINVAL; - return val; + return mapping.map_to; } static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile) { - int val; + struct smu_11_0_cmn2aisc_mapping mapping; + if (profile > PP_SMC_POWER_PROFILE_CUSTOM) return -EINVAL; - val = vega20_workload_map[profile]; + mapping = vega20_workload_map[profile]; + if (!(mapping.valid_mapping)) + return -EINVAL; - return val; + return mapping.map_to; } static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables) |