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| author | Jeffrey Hugo <quic_jhugo@quicinc.com> | 2023-12-08 09:31:01 -0700 |
|---|---|---|
| committer | Jeffrey Hugo <quic_jhugo@quicinc.com> | 2023-12-15 10:40:37 -0700 |
| commit | 4c8874c2a6512b9fe7285cab1a6910d9211a6cfb (patch) | |
| tree | 8b003283522ed54068cd49e002e2c8b5dfb2fb91 /drivers/gpu/drm/bridge | |
| parent | c8b6f4ad2ff9c6d88cdeb9acf16d0c4a323dd499 (diff) | |
| download | linux-stable-4c8874c2a6512b9fe7285cab1a6910d9211a6cfb.tar.gz linux-stable-4c8874c2a6512b9fe7285cab1a6910d9211a6cfb.tar.bz2 linux-stable-4c8874c2a6512b9fe7285cab1a6910d9211a6cfb.zip | |
accel/qaic: Implement quirk for SOC_HW_VERSION
The SOC_HW_VERSION register in the BHI space is not correctly initialized
by the device and in many cases contains uninitialized data. The register
could contain 0xFFFFFFFF which is a special value to indicate a link
error in PCIe, therefore if observed, we could incorrectly think the
device is down.
Intercept reads for this register, and provide the correct value - every
production instance would read 0x60110200 if the device was operating as
intended.
Fixes: a36bf7af868b ("accel/qaic: Add MHI controller")
Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Reviewed-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com>
Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231208163101.1295769-3-quic_jhugo@quicinc.com
Diffstat (limited to 'drivers/gpu/drm/bridge')
0 files changed, 0 insertions, 0 deletions