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| author | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2019-07-24 17:18:12 -0700 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-07-25 07:30:41 +0100 |
| commit | 4ca8d2ef8dab4ad61347e52174b870c44f1508a3 (patch) | |
| tree | 204021b082c1f6a0e3060202abaa6ede322197e4 /drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | |
| parent | 9cb27945570567b75af7a8751803d41d0a6ce1a7 (diff) | |
| download | linux-stable-4ca8d2ef8dab4ad61347e52174b870c44f1508a3.tar.gz linux-stable-4ca8d2ef8dab4ad61347e52174b870c44f1508a3.tar.bz2 linux-stable-4ca8d2ef8dab4ad61347e52174b870c44f1508a3.zip | |
drm/i915/uc: Plumb the gt through fw_upload
The gt is our new central structure for uc-related code, so we can use
that instead of jumping back to i915 via the fw object. Since we have it
in the upload function it is easy to pass it through the lower levels of
the xfer process instead of continuosly jumping via uc_fw->uc->gt, which
will also make things a bit cleaner for the next patch.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190725001813.4740-8-daniele.ceraolospurio@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 32 |
1 files changed, 12 insertions, 20 deletions
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c index 7d2d2eb94d22..2e7ac8863728 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c @@ -34,10 +34,17 @@ void intel_huc_fw_init_early(struct intel_huc *huc) intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC, huc_to_gt(huc)->i915); } -static int huc_xfer_ucode(struct intel_huc *huc) +/** + * huc_fw_xfer() - DMA's the firmware + * @huc_fw: the firmware descriptor + * + * Transfer the firmware image to RAM for execution by the microcontroller. + * + * Return: 0 on success, non-zero on failure + */ +static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct intel_gt *gt) { - struct intel_uc_fw *huc_fw = &huc->fw; - struct intel_uncore *uncore = huc_to_gt(huc)->uncore; + struct intel_uncore *uncore = gt->uncore; unsigned long offset = 0; u32 size; int ret; @@ -47,7 +54,7 @@ static int huc_xfer_ucode(struct intel_huc *huc) intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); /* Set the source address for the uCode */ - offset = intel_uc_fw_ggtt_offset(huc_fw) + + offset = intel_uc_fw_ggtt_offset(huc_fw, gt->ggtt) + huc_fw->header_offset; intel_uncore_write(uncore, DMA_ADDR_0_LOW, lower_32_bits(offset)); @@ -82,21 +89,6 @@ static int huc_xfer_ucode(struct intel_huc *huc) } /** - * huc_fw_xfer() - DMA's the firmware - * @huc_fw: the firmware descriptor - * - * Transfer the firmware image to RAM for execution by the microcontroller. - * - * Return: 0 on success, non-zero on failure - */ -static int huc_fw_xfer(struct intel_uc_fw *huc_fw) -{ - struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw); - - return huc_xfer_ucode(huc); -} - -/** * intel_huc_fw_upload() - load HuC uCode to device * @huc: intel_huc structure * @@ -110,5 +102,5 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw) */ int intel_huc_fw_upload(struct intel_huc *huc) { - return intel_uc_fw_upload(&huc->fw, huc_fw_xfer); + return intel_uc_fw_upload(&huc->fw, huc_to_gt(huc), huc_fw_xfer); } |