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author | Chris Wilson <chris@chris-wilson.co.uk> | 2018-09-03 16:02:16 +0100 |
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committer | Chris Wilson <chris@chris-wilson.co.uk> | 2018-09-03 17:55:07 +0100 |
commit | 46223993c2e4fbbb5bd35b5abef0c6b663ebba58 (patch) | |
tree | 36659eb32f5f5ba54502fcedebcb9bff16fb13f4 /drivers/gpu/drm/i915/i915_gem_execbuffer.c | |
parent | 34f89904b01e6d0cc7425d040ffa38f37d218725 (diff) | |
download | linux-stable-46223993c2e4fbbb5bd35b5abef0c6b663ebba58.tar.gz linux-stable-46223993c2e4fbbb5bd35b5abef0c6b663ebba58.tar.bz2 linux-stable-46223993c2e4fbbb5bd35b5abef0c6b663ebba58.zip |
drm/i915: Fix up FORCE_GPU_RELOC (debug) to flush CPU write domains
We currently assert that if the target is in a CPU write domain, we use
a CPU reloc path rather than the GPU reloc path. However, we have a debug
override to force the GPU path and that unfortunately hits the assert.
Include the async clflush under the debug option to ensure correct
behaviour even when debugging, and strict when not.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180903150216.19965-1-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_execbuffer.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_execbuffer.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 43706c1db31a..7d0b3a2c30e2 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1127,6 +1127,13 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, u32 *cmd; int err; + if (DBG_FORCE_RELOC == FORCE_GPU_RELOC) { + obj = vma->obj; + if (obj->cache_dirty & ~obj->cache_coherent) + i915_gem_clflush_object(obj, 0); + obj->write_domain = 0; + } + GEM_BUG_ON(vma->obj->write_domain & I915_GEM_DOMAIN_CPU); obj = i915_gem_batch_pool_get(&eb->engine->batch_pool, PAGE_SIZE); |