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author | Chris Wilson <chris@chris-wilson.co.uk> | 2017-01-09 16:16:13 +0000 |
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committer | Chris Wilson <chris@chris-wilson.co.uk> | 2017-01-10 08:12:22 +0000 |
commit | 91d4e0aa923e13ef832e9d793b6d080b6318f2d9 (patch) | |
tree | 43f0e6a8f94230f0ddedebc2eb64fd3f5ffc5fec /drivers/gpu/drm/i915/i915_gem_tiling.c | |
parent | cea84d16c3da717e99ea43108ca50bcc72ff50a1 (diff) | |
download | linux-stable-91d4e0aa923e13ef832e9d793b6d080b6318f2d9.tar.gz linux-stable-91d4e0aa923e13ef832e9d793b6d080b6318f2d9.tar.bz2 linux-stable-91d4e0aa923e13ef832e9d793b6d080b6318f2d9.zip |
drm/i915: Move ggtt fence/alignment to i915_gem_tiling.c
Rename i915_gem_get_ggtt_size() and i915_gem_get_ggtt_alignment() to
i915_gem_fence_size() and i915_gem_fence_alignment() respectively to
better match usage. Similarly move the pair of functions into
i915_gem_tiling.c next to the fence restrictions.
Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170109161613.11881-6-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_tiling.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_tiling.c | 85 |
1 files changed, 77 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index 23a896cd934f..30cb869759fb 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -58,6 +58,75 @@ * invovlement. */ +/** + * i915_gem_fence_size - required global GTT size for a fence + * @i915: i915 device + * @size: object size + * @tiling: tiling mode + * @stride: tiling stride + * + * Return the required global GTT size for a fence (view of a tiled object), + * taking into account potential fence register mapping. + */ +u32 i915_gem_fence_size(struct drm_i915_private *i915, + u32 size, unsigned int tiling, unsigned int stride) +{ + u32 ggtt_size; + + GEM_BUG_ON(!size); + + if (tiling == I915_TILING_NONE) + return size; + + GEM_BUG_ON(!stride); + + if (INTEL_GEN(i915) >= 4) { + stride *= i915_gem_tile_height(tiling); + GEM_BUG_ON(stride & 4095); + return roundup(size, stride); + } + + /* Previous chips need a power-of-two fence region when tiling */ + if (IS_GEN3(i915)) + ggtt_size = 1024*1024; + else + ggtt_size = 512*1024; + + while (ggtt_size < size) + ggtt_size <<= 1; + + return ggtt_size; +} + +/** + * i915_gem_fence_alignment - required global GTT alignment for a fence + * @i915: i915 device + * @size: object size + * @tiling: tiling mode + * @stride: tiling stride + * + * Return the required global GTT alignment for a fence (a view of a tiled + * object), taking into account potential fence register mapping. + */ +u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size, + unsigned int tiling, unsigned int stride) +{ + GEM_BUG_ON(!size); + + /* + * Minimum alignment is 4k (GTT page size), but might be greater + * if a fence register is needed for the object. + */ + if (INTEL_GEN(i915) >= 4 || tiling == I915_TILING_NONE) + return 4096; + + /* + * Previous chips need to be aligned to the size of the smallest + * fence register that can contain the object. + */ + return i915_gem_fence_size(i915, size, tiling, stride); +} + /* Check pitch constriants for all chips & tiling formats */ static bool i915_tiling_ok(struct drm_i915_private *dev_priv, @@ -126,11 +195,11 @@ static bool i915_vma_fence_prepare(struct i915_vma *vma, if (!i915_vma_is_map_and_fenceable(vma)) return true; - size = i915_gem_get_ggtt_size(i915, vma->size, tiling_mode, stride); + size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride); if (vma->node.size < size) return false; - alignment = i915_gem_get_ggtt_alignment(i915, vma->size, tiling_mode, stride); + alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride); if (vma->node.start & (alignment - 1)) return false; @@ -276,12 +345,12 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, if (!i915_vma_is_ggtt(vma)) break; - vma->fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size, - args->tiling_mode, - args->stride); - vma->fence_alignment = i915_gem_get_ggtt_alignment(dev_priv, vma->size, - args->tiling_mode, - args->stride); + vma->fence_size = i915_gem_fence_size(dev_priv, vma->size, + args->tiling_mode, + args->stride); + vma->fence_alignment = i915_gem_fence_alignment(dev_priv, vma->size, + args->tiling_mode, + args->stride); if (vma->fence) vma->fence->dirty = true; |